Fully asynchronous interface with programmable metastability settling time synchronizer
First Claim
1. A circuit for synchronizing an input signal according to a sample clock, said circuit comprising:
- a first latch for receiving said input signal and clocked by said sample clock;
a second latch for receiving said input signal and clocked by said sample clock;
a third latch for receiving said input signal and clocked by said sample clock;
a multiplexing circuit for receiving outputs originating from said first latch, said second latch and said third latch, said multiplexing circuit for outputting one of said outputs for sampling in response to read enable signals;
write enable circuitry for generating write enable signals, said write enable signals coupled to said first latch, said second latch and said third latch; and
wherein for a given clock cycle, said write enable signals enable a single one of said first, second and third latches for receiving said input signal and said read enable signals enable another single one of said first, second and third latches for outputting through said multiplexing circuit.
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Abstract
A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.
67 Citations
19 Claims
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1. A circuit for synchronizing an input signal according to a sample clock, said circuit comprising:
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a first latch for receiving said input signal and clocked by said sample clock; a second latch for receiving said input signal and clocked by said sample clock; a third latch for receiving said input signal and clocked by said sample clock; a multiplexing circuit for receiving outputs originating from said first latch, said second latch and said third latch, said multiplexing circuit for outputting one of said outputs for sampling in response to read enable signals; write enable circuitry for generating write enable signals, said write enable signals coupled to said first latch, said second latch and said third latch; and wherein for a given clock cycle, said write enable signals enable a single one of said first, second and third latches for receiving said input signal and said read enable signals enable another single one of said first, second and third latches for outputting through said multiplexing circuit. - View Dependent Claims (2, 3, 4, 5)
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6. A circuit for synchronizing an input signal according to a sample clock, said circuit comprising:
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a plurality of n latches, each latch for receiving said input signal in parallel and each latch clocked by said sample clock in parallel; a multiplexing circuit for receiving n outputs originating from said plurality of n latches, said multiplexing circuit responsive to read enable signals for outputting one of said n outputs for sampling; write enable circuitry for generating write enable signals, said write enable signals coupled to said plurality of n latches; and wherein for a given sample clock cycle said write enable signals enable a single one of said plurality of n latches for receiving said input signal and said read enable signals enable another single one of said plurality of n latches for outputting through said multiplexing circuit. - View Dependent Claims (7, 8, 9, 10)
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11. A synchronizer having programmable metastability settling time for synchronizing an input signal according to a sample clock, said synchronizer comprising:
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a plurality of n latches, each latch for receiving said input signal in parallel and each latch clocked by said sample clock in parallel; a multiplexing circuit for receiving n outputs originating from said plurality of n latches, said multiplexing circuit responsive to read enable signals for outputting one of said n outputs for sampling;
write enable circuitry for generating write enable signals, said write enable signals coupled to said plurality of n latches, wherein said write enable circuitry receives program signals and in response thereto generates said write enable signals such that x number of latches, of said plurality of n latches, are used wherein x is equal to or less than 4c; andwherein for a given sample clock cycle, said write enable signals enable a single one of said plurality of n latches for receiving said input signal and said read enable signals enable another single one of said plurality of n latches for outputting through said multiplexing circuit. - View Dependent Claims (12, 13, 14)
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15. A system including a synchronizing circuit for synchronizing an input signal according to a sample clock, said system comprising:
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a writing system for writing said input signal for transmission, said writing system synchronized to a write clock; a reading system for reading said input signal synchronized to said sample clock; said writing system coupled to said synchronizing circuit and said reading system coupled to said synchronizing circuit wherein said write clock and said sample clock are asynchronous; and said synchronizing circuit comprising; (a) a plurality of n latches, each latch for receiving said input signal in parallel and each latch clocked in parallel by said sample clock; (b) a multiplexing circuit for receiving n outputs originating from said plurality of n latches, said multiplexing circuit for outputting one of said n outputs for sampling according to read enable signals; (c) write enable circuitry for generating write enable signals, said write enable signals coupled to said plurality of n latches; and (d) wherein for a given sample clock cycle, said write enable signals enable a single one of said plurality of n latches for receiving said input signal and said read enable signals enable another single one of said plurality of n latches for outputting through said multiplexing circuit. - View Dependent Claims (16, 17, 18, 19)
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Specification