Driver circuits for switching transistors

• US 5,598,118 A
• Filed: 10/21/1994
• Issued: 01/28/1997
• Est. Priority Date: 11/05/1993
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Koifman, Vladimir, Afek, Yachin, Kashat, Israel
• Primary Examiner(s): Tran, Toan
• Application Number:
  US08/326,910
• Time in Patent Office: 830 Days
• Field of Search: 327/58-62, 327/65, 327/74, 327/108, 327/111, 327/403-405, 327/407-413, 327/427, 327/434-437, 327/574, 327/581, 327/337, 327/554, 327/148, 327/390, 327/536 , 327/589
• US Class Current: 327/108
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A driver circuit (8) is arranged to switch a transistor (10) of a switched capacitor circuit, or transistors (62 and 64) of a differential switched capacitor circuit, between a first state, in which the transistor switch is closed whereby an input signal (VINP) is transferred to an output, and a second state, in which the transistor switch is open. The driver circuit includes a maximum and a minimum selection (12, 14) between the input signal and a reference voltage (VAG) , a voltage shift element (26), and switches (16, 18, 20, 22, 24), coupled to receive the input signal (VINP) and to the gate electrode of the transistor switch (10), which ensures that the gate-to-source voltage of the transistor switch (10), in the first and second states, is independent of the input signal (VINP).

Claims

1. A driver circuit for switching a transistor from a first state in which the transistor switch is closed such that an input signal is transferred to an output and a second state in which the transistor switch is open, the driver circuit comprises:

a first reference node for receiving a first reference voltage signal;

a second reference node for receiving a second reference voltage signal;

maximum detection means coupled to receive the input signal and the first reference voltage signal and for providing at an output the greater of the two signals, the output of the maximum detection means being selectively coupled to the gate electrode of the transistor switch;

minimum detection means coupled to receive the input signal and the first reference voltage signal and for providing at an output the lesser of the two signals;

voltage shifting means having an input selectively coupled to the second reference node and to the output of the minimum detection means and an output coupled to the gate electrode of the transistor switch;

wherein in the second state the output of the maximum detection means is coupled to the gate electrode of the transistor switch and the output of the voltage shifting means and the input of the voltage shifting means is coupled to the second reference voltage signal, and wherein in the first state, the output of the minimum detection means is coupled to the input of the voltage shifting means such that the output of the voltage shifting means is shifted by the minimum output signal to a voltage level which corresponds to the difference between the second reference voltage signal and the minimum output signal such that the voltage on the gate electrode of the transistor switch is dependent on the maximum output signal and the signal at the output of the voltage shifting means, whereby the gate-to-source voltage of the transistor switch is independent of the input signal.

2. A driver circuit according to claim 1 wherein the driver circuit switches the transistor switch between the first state and the second state in response to a switching signal have a first signal level and a second signal level respectively, and wherein the driver circuit further comprises:

a first switch coupled to receive the switching signal and coupled between the output of the maximum detection means and the gate electrode of the transistor switch such that when the switching signal has the second signal level the first switch is closed and the maximum output signal is coupled to the gate electrode and when the switching signal has the first signal level the first switch is open; and

a second switch coupled to receive the inverse of the switching signal and coupled between the output of the minimum detection means and the input of the voltage shifting means such that when the switching signal has the second signal level, the second switch is open and when the switching signal has the first signal level, the second switch is closed and the minimum output signal is coupled to the input of the voltage shifting means.

3. A driver circuit according to claim 2 wherein the first switch comprises:

a first transistor of a first conductivity type and having a first current electrode coupled to the output of the maximum detection means, a second current electrode coupled to the gate electrode of the transistor switch, a bulk electrode coupled to the first current electrode and a gate electrode;

a second transistor of the first conductivity type having a first current electrode coupled to the output of the maximum detection means, a second current electrode coupled to the gate electrode of the first transistor, a bulk electrode coupled to the bulk electrode of the first transistor and a gate electrode coupled to receive the switching signal; and

a third transistor of a second conductivity type having a first current electrode coupled to the gate electrode of the first transistor, a second current electrode coupled to a third reference voltage supply and a gate electrode coupled to receive the switching signal.

4. A driver circuit according to claim 2 further comprising a third switch coupled to receive the inverted switching signal and coupled between the second reference node and the input of the voltage shifting means such that when the switching signal has the second signal level, the third switch is closed and the second reference voltage signal is coupled to the input of the voltage shifting means and when the switching signal has the first signal level, the third switch is open.

5. A driver circuit according to claim 1 wherein the voltage shifting means comprises a capacitor, one plate forming the input of the voltage shifting means and the other plate forming the output of the voltage shifting means.

6. A driver circuit according to claim 1 wherein the maximum detection means has a first input for receiving the input signal and a second input for receiving the first reference voltage signal and comprises:

a first transistor having a first current electrode coupled to the second reference voltage node, a second current electrode coupled to a node and a gate electrode coupled to the first input;

a second transistor having a first current electrode coupled to the second reference voltage node, a second current electrode coupled to the node and a gate electrode coupled to the second input;

a third diode-coupled transistor having a first current electrode coupled to the node, a gate electrode and a second current electrode coupled to the second reference voltage node, the gate electrode and the output of the maximum detection means; and

a current supply means for supplying a current to the node such that the first and second transistors operate in the sub-threshold region whereby the greater of the voltage signals at the first and second inputs is mirrored to the output of the maximum detection means.

8. A driver circuit according to claim 1 wherein the minimum detection means has a first input for receiving the input signal and a second input for receiving the first reference voltage signal and comprises:

a first transistor having a first current electrode coupled to a third reference voltage node, a second current electrode coupled to a node and a gate electrode coupled to the first input;

a second transistor having a first current electrode coupled to the third reference voltage node, a second current electrode coupled to the node and a gate electrode coupled to the second input;

a third diode-coupled transistor having a first current electrode coupled to the node, a gate electrode and a second current electrode coupled to the third reference voltage node, the gate electrode and the output of the minimum detection means; and

a current supply means for supplying a current to the node such that the first and second transistors operate in the sub-threshold region whereby the smaller of the voltage signals at the first and second inputs is mirrored to the output of the minimum detection means.

7. A driver circuit according to claim I wherein the maximum detection means has a first input for receiving the input signal and a second input for receiving the first reference voltage signal and comprises:

a first transistor having a first current electrode, a second current electrode coupled to a third reference voltage node and a gate electrode coupled to the first input;

a second transistor having a first current electrode coupled to the output of the maximum detection means, a second current electrode coupled to the first current electrode of the first transistor and a gate electrode coupled to the second input;

a current supply means coupled to the first current electrode of the second transistor for supplying current thereto such that the first and second transistors operate in the sub-threshold region whereby the greater of the voltage signals at the first and second inputs is outputted to the output of the maximum detection means.

9. A driver circuit for a differential switched capacitor circuit, the driver circuit being arranged to switch a pair of differential transistor switches from a first state in which the switches are closed such that respective first and second input signals, which form therebetween a differential input signal, are transferred to first and second outputs thereof and a second state in which the switches are open, the driver circuit comprising:

a first reference node for receiving a first reference voltage signal, the first reference voltage signal having a level substantially equal to half the sum of the first and second input signals;

a second reference node for receiving a second reference voltage signal;

first maximum detection means coupled to receive the first input signal and the first reference voltage signal and for providing at an output the greater of the two signals, the output of the first maximum detection means being selectively coupled to the gate electrode of a first transistor switch of the pair of transistor switches;

second maximum detection means coupled to receive the second input signal and the first reference voltage signal and for providing at an output the greater of the two signals, the output of the second maximum detection means being selectively coupled to the gate electrode of a second transistor switch of the pair;

first voltage shifting means having an input selectively coupled between the second reference node and the output of the second maximum detection means and an output coupled to the gate electrode of the first transistor switch;

second voltage shifting means having an input selectively coupled between the second reference node and the output of the first maximum detection means and an output coupled to the gate electrode of the second transistor switch;

wherein in the second state the output of the first maximum detection means is coupled to the gate electrode of the first transistor switch, the output of the first voltage shifting means and the input of the second voltage shifting means and the output of the second maximum detection means is coupled to the gate electrode of the second transistor switch, the output of the second voltage shifting means and the input of the first voltage shifting means, and

wherein in the first state, the inputs of the first and second voltage shifting means are coupled to the second reference node such that the outputs of the first and second voltage shifting means are each shifted by the second reference voltage signal to voltage levels which correspond to the difference between the second maximum output signal and the second reference voltage signal, and the first maximum output signal and the second reference voltage signal, respectively, such that the voltages on the gate electrodes of the first and second transistor switches are dependent on the first maximum output signal and the output of the first voltage shifting means, and second maximum output signal and the output of the second voltage shifting means, respectively, whereby the gate-to-source voltages of the first and second transistor switches are independent of the differential input signal.

10. A driver circuit according to claim 9 wherein the driver circuit switches the first and second transistor switches between the first state and the second state in response to a switching signal have a first signal level and a second signal level respectively, and wherein the driver circuit further comprises:

a first switch coupled to receive the switching signal and coupled between the output of the first maximum detection means and the gate electrode of the first transistor switch such that when the switching signal has the second signal level, the first switch is closed and the first maximum output signal is coupled to the gate electrode of the first transistor switch and when the switching signal has the first signal level, the first switch is open;

a second switch coupled to receive the switching signal and coupled between the output of the second maximum detection means and the gate electrode of the second transistor switch such that when the switching signal has the second signal level, the second switch is closed and the second maximum output signal is coupled to the gate electrode of the second transistor switch and when the switching signal has the second signal level, the second switch is open;

third switch means coupled to receive the inverse of the switching signal and coupled between the output of the second maximum detection means and the input of the first voltage shifting means and between the second reference node and the input of the first voltage shifting means, such that when the switching signal has the second signal level, the second maximum output signal is coupled to the input of the first voltage shifting means and when the switching signal has the first signal level, the second reference voltage signal is coupled to the input of the first voltage shifting means; and

fourth switch means coupled to receive the inverse of the switching signal and coupled between the output of the first maximum detection means and the input of the second voltage shifting means and between the second reference node and the input of the second voltage shifting means, such that when the switching signal has the second signal level, the first maximum output signal is coupled to the input of the second voltage shifting means and when the switching signal has the first signal level, the second reference voltage signal is coupled to the input of the second voltage shifting means.

11. A driver circuit according to claim 10 wherein the first switch comprises:

a first transistor of a first conductivity type and having a first current electrode coupled to the output of the first maximum detection means, a second current electrode coupled to the gate electrode of the first transistor switch, a bulk electrode coupled to the first current electrode and a gate electrode;

a second transistor of the first conductivity type having a first current electrode coupled to the output of the first maximum detection means, a second current electrode coupled to the gate electrode of the first transistor, a bulk electrode coupled to the bulk electrode of the first transistor and a gate electrode coupled to receive the switching signal; and

a third transistor of a second conductivity type having a first current electrode coupled to the gate electrode of the first transistor, a second current electrode coupled to the second reference node and a gate electrode coupled to receive the switching signal, and

wherein the second switch comprises;

a fourth transistor of the first conductivity type and having a first current electrode coupled to the output of the second maximum detection means, a second current electrode coupled to the gate electrode of the second transistor switch, a bulk electrode coupled to the first current electrode and a gate electrode;

a fifth transistor of the first conductivity type having a first current electrode coupled to the output of the second maximum detection means, a second current electrode coupled to the gate electrode of the fourth transistor, a bulk electrode coupled to the bulk electrode of the fourth transistor and a gate electrode coupled to receive the switching signal; and

a sixth transistor of the second conductivity type having a first current electrode coupled to the gate electrode of the fourth transistor, a second current electrode coupled to the second reference node and a gate electrode coupled to receive the switching signal.

12. A driver circuit according to claim 10 wherein the third switch means comprises:

a first transistor of the first conductivity type having a first current electrode coupled to the output of the second maximum detection means, a second current electrode coupled to the input of the first voltage shifting means and a gate electrode coupled to receive the inverse of the switching signal; and

a second transistor of the second conductivity type having a first current electrode coupled to the input of the first voltage shifting means, a second current electrode coupled to the second reference voltage node and a gate electrode coupled to receive the inverse of the switching signal, and

wherein the fourth switch means comprises;

a third transistor of the first conductivity type having a first current electrode coupled to the output of the first maximum detection means, a second current electrode coupled to the input of the second voltage shifting means and a gate electrode coupled to receive the inverse of the switching signal; and

a fourth transistor of the second conductivity type having a first current electrode coupled to the input of the second voltage shifting means, a second current electrode coupled to the second reference voltage node and a gate electrode coupled to receive the inverse of the switching signal.

13. A driver circuit according to claim 9 wherein the each one of the first and second voltage shifting means comprise a capacitor, one plate forming the input of the voltage shifting means and the other plate forming the output of the voltage shifting means.

14. A driver circuit according to claim 9 wherein the first and second maximum detection means each have a first input for receiving the respective input signal and a second input for receiving the first reference voltage signal and comprises:

a first transistor having a first current electrode coupled to a third reference voltage node, a second current electrode coupled to a node and a gate electrode coupled to the first input;

a second transistor having a first current electrode coupled to the third reference voltage node, a second current electrode coupled to the node and a gate electrode coupled to the second input;

a third diode-coupled transistor having a first current electrode coupled to the node, a gate electrode and a second current electrode coupled to the third reference voltage node, the gate electrode and the output of the maximum detection means; and

a current supply means for supplying a current to the node such that the first and second transistors operate in the sub-threshold region whereby the greater of the voltage signals at the first and second inputs is mirrored to the output of the maximum detection means.

15. A driver circuit according to claim 9 wherein the first and second maximum detection means each have a first input for receiving the respective input signal and a second input for receiving the first reference voltage signal and comprises:

a first transistor having a first current electrode, a second current electrode coupled to the second reference voltage node and a gate electrode coupled to the first input;

a second transistor having a first current electrode coupled to the output of the maximum detection means, a second current electrode coupled to the first current electrode of the first transistor and a gate electrode coupled to the second input;

a current supply means coupled to the first current electrode of the second transistor for supplying current thereto such that the first and second transistors operate in the sub-threshold region whereby the greater of the voltage signals at the first and second inputs is outputted to the output of the maximum detection means.

16. A driver circuit for a differential switched capacitor circuit, the driver circuit being arranged to switch a pair of differential transistor switches from a first state in which the switches are closed such that respective first and second input signals, which form therebetween a differential input signal, are transferred to first and second outputs thereof and a second state in which the switches are open, the driver circuit comprising:

a first reference node for receiving a first reference voltage signal, the first reference voltage signal having a level substantially equal to half the sum of the first and second input signals;

a second reference node for receiving a second reference voltage signal;

first minimum detection means coupled to receive the first input signal and the first reference voltage signal and for providing at an output the lesser of the two signals, the output of the first minimum detection means being selectively coupled to the gate electrode of a first transistor switch of the pair of transistor switches;

second minimum detection means coupled to receive the second input signal and the first reference voltage signal and for providing at an output the lesser of the two signals, the output of the second minimum detection means being selectively coupled to the gate electrode of a second transistor switch of the pair;

first voltage shifting means having an input selectively coupled between the second reference node and the output of the second minimum detection means and an output coupled to the gate electrode of the first transistor switch;

second voltage shifting means having an input selectively coupled between the second reference node and the output of the first minimum detection means and an output coupled to the gate electrode of the second transistor switch;

wherein in the second state the output of the first minimum detection means is coupled to the gate electrode of the first transistor switch, the output of the first voltage shifting means and the input of the second voltage shifting means and the output of the second minimum detection means is coupled to the gate electrode of the second transistor switch, the output of the second voltage shifting means and the input of the first voltage shifting means, and

wherein in the first state, the inputs of the first and second voltage shifting means are coupled to the second reference node such that the outputs of the first and second voltage shifting means are each shifted by the second reference voltage signal to voltage levels which correspond to the difference between the second minimum output signal and the second reference voltage signal, and the first minimum output signal and the second reference voltage signal, respectively, such that the voltages on the gate electrodes of the first and second transistor switches are dependent on the first minimum output signal and the output of the first voltage shifting means, and second minimum output signal and the output of the second voltage shifting means, respectively, whereby the gate-to-source voltages of the first and second transistor switches are independent of the differential input signal.

17. A driver circuit according to claim 16 wherein the driver circuit switches the first and second transistor switches between the first state and the second state in response to a switching signal have a first signal level and a second signal level respectively, and wherein the driver circuit further comprises:

a first switch coupled to receive the switching signal and coupled between the output of the first minimum detection means and the gate electrode of the first transistor switch such that when the switching signal has the second signal level, the first switch is closed and the first minimum output signal is coupled to the gate electrode of the first transistor switch and when the switching signal has the first signal level, the first switch is open;

a second switch coupled to receive the switching signal and coupled between the output of the second minimum detection means and the gate electrode of the second transistor switch such that when the switching signal has the second signal level, the second switch is closed and the second minimum output signal is coupled to the gate electrode of the second transistor switch and when the switching signal has the second signal level, the second switch is open;

third switch means coupled to receive the inverse of the switching signal and coupled between the output of the second minimum detection means and the input of the first voltage shifting means and between the second reference node and the input of the first voltage shifting means, such that when the switching signal has the second signal level, the second minimum output signal is coupled to the input of the first voltage shifting means and when the switching signal has the first signal level, the second reference voltage signal is coupled to the input of the first voltage shifting means; and

fourth switch means coupled to receive the inverse of the switching signal and coupled between the output of the first minimum detection means and the input of the second voltage shifting means and between the second reference node and the input of the second voltage shifting means, such that when the switching signal has the second signal level, the first minimum output signal is coupled to the input of the second voltage shifting means and when the switching signal has the first signal level, the second reference voltage signal is coupled to the input of the second voltage shifting means.

18. A driver circuit according to claim 17 wherein the first switch comprises:

a first transistor of a first conductivity type and having a first current electrode coupled to the output of the first minimum detection means, a second current electrode coupled to the gate electrode of the first transistor switch, a bulk electrode coupled to the first current electrode and a gate electrode;

a second transistor of the first conductivity type having a first current electrode coupled to the output of the first minimum detection means, a second current electrode coupled to the gate electrode of the first transistor, a bulk electrode coupled to the bulk electrode of the first transistor and a gate electrode coupled to receive the switching signal; and

a third transistor of a second conductivity type having a first current electrode coupled to the gate electrode of the first transistor, a second current electrode coupled to the second reference node and a gate electrode coupled to receive the switching signal, and

wherein the second switch comprises;

a fourth transistor of the first conductivity type and having a first current electrode coupled to the output of the second minimum detection means, a second current electrode coupled to the gate electrode of the second transistor switch, a bulk electrode coupled to the first current electrode and a gate electrode;

a fifth transistor of the first conductivity type having a first current electrode coupled to the output of the second minimum detection means, a second current electrode coupled to the gate electrode of the fourth transistor, a bulk electrode coupled to the bulk electrode of the fourth transistor and a gate electrode coupled to receive the switching signal; and

a sixth transistor of the second conductivity type having a first current electrode coupled to the gate electrode of the fourth transistor, a second current electrode coupled to the second reference node and a gate electrode coupled to receive the switching signal.

19. A driver circuit according to claim 17 wherein the third switch means comprises:

a first transistor of the first conductivity type having a first current electrode coupled to the output of the second minimum detection means, a second current electrode coupled to the input of the first voltage shifting means and a gate electrode coupled to receive the inverse of the switching signal; and

a second transistor of the second conductivity type having a first current electrode coupled to the input of the first voltage shifting means, a second current electrode coupled to the second reference voltage node and a gate electrode coupled to receive the inverse of the switching signal, and

wherein the fourth switch means comprises;

a third transistor of the first conductivity type having a first current electrode coupled to the output of the first minimum detection means, a second current electrode coupled to the input of the second voltage shifting means and a gate electrode coupled to receive the inverse of the switching signal; and

a fourth transistor of the second conductivity type having a first current electrode coupled to the input of the second voltage shifting means, a second current electrode coupled to the second reference voltage node and a gate electrode coupled to receive the inverse of the switching signal.

20. A driver circuit according to claim 16 wherein the each one of the first and second voltage shifting means comprise a capacitor, one plate forming the input of the voltage shifting means and the other plate forming the output of the voltage shifting means.

21. A driver circuit according to claim 16 wherein the first and second minimum detection means each have a first input for receiving the respective input signal and a second input for receiving the first reference voltage signal and comprises:

a first transistor having a first current electrode coupled to the second reference voltage node, a second current electrode coupled to a node and a gate electrode coupled to the first input;

a second transistor having a first current electrode coupled to the second reference voltage node, a second current electrode coupled to the node and a gate electrode coupled to the second input;

a third diode-coupled transistor having a first current electrode coupled to the node, a gate electrode and a second current electrode coupled to the second reference voltage node, the gate electrode and the output of the minimum detection means; and

a current supply means for supplying a current to the node such that the first and second transistors operate in the sub-threshold region whereby the smaller of the voltage signals at the first and second inputs is mirrored to the output of the minimum detection means.