Trench EPROM

• US 5,598,367 A
• Filed: 06/07/1995
• Issued: 01/28/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/481,675
• Time in Patent Office: 601 Days
• Field of Search: 365/149, 365/185.01, 365/185.18, 365/185.33, 257/314, 257/315
• US Class Current: 365/149
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A two-device nonvolatile memory cell is described. The cell comprises a planar FET and a vertical FET in series. The vertical FET has a floating gate that is predominantly capacitively coupled to a buried n well that serves as the control electrode. The structure is very similar to a trench DRAM cell, and the nonvolatile memory cell can be integrated onto a DRAM chip.

Claims

1. A semiconductor chip comprising:

a semiconductor substrate having a planar surface and a first substrate region;

a first FET having a first gate adjacent a first gate insulator adjacent a first channel in said first substrate region and a first and a second diffused region; and

a second FET connected in series with said first FET, said second FET having a second gate adjacent a second gate insulator adjacent a second channel in said first substrate region, said second gate floating and not connected to said first gate, said second gate predominantly capacitively coupled to a control electrode, said control electrode being a third diffused region.

2. A semiconductor chip as recited in claim 1, wherein said second FET comprises said second diffused region and said third diffused region, said channel therebetween.

3. A semiconductor chip as recited in claim 2, wherein said third diffused region is buried.

4. A semiconductor chip as recited in claim 3, further comprising a trench having a sidewall intersecting said second diffused region and said third diffused region, said first gate being on said planar surface, said second gate being along said sidewall.

5. A semiconductor chip as recited in claim 1, further comprising a wordline and a bitline, said first gate connected to said word line, said first diffused region connected to said bit line.

6. A semiconductor chip as recited in claim 1, said chip further comprising a trench DRAM cell.

7. A semiconductor chip as recited in claim 6, said first FET and said second FET comprising a non-volatile memory cell wherein said non-volatile memory cell and said DRAM memory cell cover substantially equal surface areas on the chip.

8. A method of using an EPROM semiconductor structure comprising the steps of:

(a) providing a high voltage on a gate and an intermediate voltage on a first diffusion of a first FET, so as to substantially provide said intermediate voltage on a second diffusion of said first FET;

(b) providing a low voltage on a buried plate coupling to a vertical floating gate of a second FET linked in series with said first FET, said vertical floating gate intersecting said second diffusion; and

wherein said high, intermediate, and low voltages being sufficient to allow Fowler-Nordheim tunneling of electrons from said floating gate to said second diffusion, leaving said second FET with a reduced Vt.

9. A method of providing a flash erase to a plurality of EPROM cells on a semiconductor structure comprising the steps of:

(a) providing an intermediate voltage on buried diffusions coupling to floating gates of vertical FETs of the EPROM cells, wherein said floating gates are predominantly capacitively coupled to said buried diffusions;

(b) providing a negative voltage on a substrate coupling to all said floating gates; and

wherein said intermediate, and negative voltages being sufficient to allow Fowler-Nordheim tunneling of electrons from said substrate to said floating gates if said floating gates had a positive charge, thereby reducing said positive charge.