Distributed write data drivers for burst access memories

• US 5,598,376 A
• Filed: 06/30/1995
• Issued: 01/28/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/497,354
• Time in Patent Office: 578 Days
• Field of Search: 365/230.01, 365/189.01, 365/230.06, 365/189.05, 365/204, 365/205, 365/233.5
• US Class Current: 365/230.06
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Claims

1. A memory device having a plurality of internal data line pairs, an equilibration control circuit and a write cycle control circuit, the memory device further comprising:

a plurality of data sense amplifiers each coupled to the equilibration control circuit, the write cycle control circuit and at least one of the data line pairs;

a plurality of write data drivers, each write data driver associated with at least one of said data sense amplifiers; and

a plurality of write data driver enable circuits, each write driver enable circuit associated with one of said write data drivers to enable said write data drivers to drive data onto at least one of the data line pairs in response to deassertion of an equilibrate signal from the equilibration control circuit while a write cycle enable signal from the write cycle control circuit is asserted.

2. The memory device of claim 1, further comprising:

a burst access control circuit adapted to receive an initial address in response to an access cycle strobe signal and to generate a series of addresses, each in response to a further transition of the access cycle strobe signal.

3. The memory device of claim 2, further comprising:

an output buffer coupled to at least one of said data sense amplifiers and to the access cycle strobe signal, said output buffer adapted to drive data from the memory device in response to a plurality of transitions of the access cycle strobe signal.

4. The memory device of claim 3, wherein the access cycle strobe signal is a column address strobe signal and the memory device is a burst extended data out dynamic random access memory device.

5. The memory device of claim 1, wherein the memory device is adapted to operate in an Extended Data Out page mode.

6. A memory device comprising:

a plurality of write data drivers comprising an enable input, a data input and a data output;

a plurality of data lines, each of said data lines coupled to the data output of at least one of said write data drivers; and

a plurality of write data driver enable circuits, each of said write data driver enable circuits adapted to receive a write cycle control signal and an equilibrate control signal, each of said write data driver enable circuits located in close proximity and coupled to the enable input of at least one of said write data drivers.

7. The memory device of claim 6, further comprising:

a plurality of data sense amplifiers, each of said data sense amplifiers being associated with one of the plurality of write data drivers.

8. The memory device of claim 7, further comprising:

a plurality of memory element subarrays, each of said subarrays coupled to at least one of said write data drivers by at least one of said data lines, and each of said subarrays coupled to at least one of said data sense amplifiers by at least one of said data lines.

9. The memory device of claim 8, further comprising:

a plurality of equilibration transistors, each of said equilibration transistors responsive to the equilibrate control signal to couple at least two of said data lines together.

10. The memory device of claim 9, wherein said write data drivers are disabled by said write data driver enable circuits while said equilibration transistors couple said data lines together.

11. A memory device comprising:

a memory element array region;

a plurality of data line pairs dispersed within said memory element array region; and

a plurality of write data drivers dispersed along an edge of said memory element array region, each comprising an equilibrate input, a write active input, a write data input and a write data output, each of said write data drivers adapted to drive a data signal from the write data input to at least one of said data line pairs.

12. The memory device of claim 11, further comprising:

a main logic region outside said array region, said main logic region comprising an equilibration control circuit adapted to provide an equilibrate signal to the equilibrate input of said write data drivers.

13. The memory device of claim 12, further comprising:

a pads and logic region outside said array region and outside said main logic region, wherein the equilibrate signal is routed from said main logic region through said pads and logic region to said write data drivers.

14. The memory device of claim 11, further comprising:

a main logic region outside said array region, said main logic region comprising a write cycle control circuit adapted to provide a write active signal to the write active input of said write data drivers.

15. The memory device of claim 14, further comprising:

a pads and logic region outside said array region and outside said main logic region, wherein the write active signal is routed from said main logic region through said pads and logic region to said write data drivers.

16. A memory device comprising:

a memory element array region;

a control circuit region, outside of said memory element array region, for generating memory control signals including an equilibrate signal and a write enable signal;

a plurality of data line pairs dispersed throughout said memory element array region;

a plurality of data sense amplifiers, said data sense amplifiers distributed along an edge of said memory element array region, each amplifier proximately located to at least one of said data line pairs; and

a distributed plurality of write data drivers each comprising an equilibrate inactive input enable responsive to the equilibrate signal and a write active input enable responsive to the write enable signal, each of said write data drivers proximately located to a data sense amplifier and associated with at least one of said data line pairs.

17. The memory device of claim 16, further comprising:

an address strobe input adapted to receive an address strobe signal; and

an address counter responsive to the address strobe signal to generate an address and to provide the address to said memory element array region.

18. A memory device comprising:

a data input;

a plurality of memory element subarrays; and

a plurality of data sense amplifiers coupled to said subarrays, each of said data sense amplifiers comprising a write data driver responsive to an active write enable signal and an inactive equilibration signal, to drive write data received on said data input to a corresponding one of said subarrays.

19. A method of storing data in a system comprising steps of:

providing a memory having a distributed plurality of data driver enable circuits;

addressing the memory;

providing data to the memory;

asserting an equilibration signal at the plurality of data driver enable circuits in response to said step of addressing;

asserting a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibration signal;

gating a write enable signal through at least one of the data driver enable circuits in response to said step of deasserting; and

storing data in a memory cell of the memory in response to said step of gating a write enable signal.