Wireless alarm system

• US 5,598,427 A
• Filed: 10/24/1991
• Issued: 01/28/1997
• Est. Priority Date: 11/02/1988
• Status: Expired due to Term

• Current Assignee: NorthPeak Wireless, LLC
• Original Assignee: Axonn LLC (Globalstar Incorporated)
• Inventors: Arthur, James D., Rouquette, Robert E., Sanderford, H. Britton Jr.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US07/782,345
• Time in Patent Office: 1,923 Days
• Field of Search: 375/1, 375/76, 375/82, 375/96, 375/103, 375/110, 375/114, 375/115, 375/200-210, 375/317-319, 375/328, 375/343, 375/350, 375/359, 375/360, 375/361, 375/365, 375/367, 380/34, 380/48
• US Class Current: 375/145
• CPC Class Codes: G08B 25/10 using wireless transmission systems G08B25/009 takes precedence
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70756 Jumping within the code, i.e. masking or slewing H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/70757 with increased resolution, i.e. higher than half a chip H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/7077 Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and data register. The spread spectrum receiver acquires synchronization of the spread spectrum signal using a microprocessor coupled to the quieting, signal strength or baseband output of the receiver, with a two step algorithm. The steps comprise achieving a coarse lock and a fine lock to the spread spectrum signal.

Claims

1. A spread spectrum chip code synchronization apparatus, coupled to a baseband output of a receiver, the spread spectrum chip code synchronization apparatus comprising:

means coupled to the baseband output of said receiver for sampling and digitizing a plurality of analog baseband signals, from the baseband output of said receiver, as a plurality of data signals, wherein each of the analog baseband signals is sampled and digitized as one of the plurality of data signals during one chip time;

register means, including a plurality of shift registers, said register means coupled to said sampling and digitizing means, for shifting the plurality of data signals sequentially through the plurality of shift registers; and

means coupled to said register means for adding in parallel each of the plurality of data signals stored in said plurality of shift registers with a respective one of a plurality of weights, as a respective result, and for adding sequentially the results as a correlation sum for attaining chip code synchronization.

2. The apparatus as set forth in claim 1 further including means coupled to said adding means for comparing the correlation sum to a predetermined threshold.

3. The apparatus as set forth in claim 2 further including means coupled to said comparing means for dithering a chip clock by at least a first portion of one chip time, thereby attaining a clock resulting in chip code synchronization.

4. The apparatus as set forth in claim 3 further including means for storing a spread spectrum chip code as the plurality of predetermined weights.

9. The apparatus as set forth in claim 1, 2, 3, 4, or 8 wherein said register means includes a recirculating register.

10. The apparatus as set forth in claims 1, 2, 3, 4, or 8 further including means for synchronizing the baseband samples so that there is one sample per chip time in place of Nyquist oversampling.

5. A method of using a processor for synchronizing the timing acquisition of a spread spectrum signal received by a receiver, comprising the steps of:

sampling and digitizing a plurality of analog baseband signals from a baseband output of said receiver, to generate a plurality of data signals, wherein each of the analog baseband signals is sampled and digitized during one chip time;

shifting the plurality of data signals sequentially through a plurality of shift registers;

adding in parallel each of the plurality of data signals stored in said plurality of shift registers with a respective one of a plurality of weights, as a respective result, and for adding sequentially the results as a correlation sum; and

using the correlation sum to attain chip code synchronization.

6. The method as set forth in claim 5 wherein the step of using the correlation sum includes the step of comparing the correlation sum to a predetermined threshold.

7. The method as set forth in claim 6 wherein the step of using the correlation sum includes the step of dithering a chip clock by at least a first portion of one chip time, thereby attaining a clock lock, resulting in chip code synchronization.

8. A spread spectrum chip code synchronization apparatus, coupled to a baseband output of a receiver, the spread spectrum chip code synchronization apparatus comprising:

means coupled to the baseband output of said receiver for sampling and digitizing a plurality of analog baseband signals from the baseband output of said receiver, to generate a plurality of data signals, wherein each of the analog baseband signals is sampled and digitized during one chip time;

register means, including a plurality of shift registers, said register means coupled to said sampling and digitizing means for shifting and recirculating the plurality of data signals sequentially through the plurality of shift registers; and

means coupled to said register means for adding sequentially the data signals passing through one of the shift registers with a respective one of a plurality of predetermined weights, as a respective result, and for adding sequentially the results as a correlation sum for attaining chip code synchronization.

11. A method of using a processor for synchronizing the timing acquisition of a spread spectrum signal received by a receiver, comprising the steps of:

sampling and digitizing a plurality of analog baseband signals from a baseband output of said receiver, to generate a plurality of data signals, wherein each of the analog baseband signals is sampled and digitized during one chip time;

shifting and recirculating the plurality of data signals sequentially through a plurality of shift registers;

adding sequentially the data signals passing through one of the shift registers according to a predetermined weighting algorithm to generate a correlation sum for attaining chip code synchronization.