Integrated circuit device having internal fast clock source

• US 5,598,447 A
• Filed: 05/10/1993
• Issued: 01/28/1997
• Est. Priority Date: 05/11/1992
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Usui, Akira
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/060,733
• Time in Patent Office: 1,359 Days
• Field of Search: 375/354, 375/356, 375/375, 375/376, 370/105.3, 326/64, 326/81, 327/147, 327/156, 331/1 A, 331/1 R, 331/17, 331/25, 331/57
• US Class Current: 375/376
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

An integrated circuit device is comprised of an input interface, a PLL unit, a processing unit and an output interface. The input interface operates in response to an external clock signal for sequentially receiving input data in synchronization with an external synchro signal. The PLL unit includes an internal clock source operative in phase-locked manner according to the external synchro signal for generating an internal clock signal which is faster than the external clock signal. The processing unit operates in response to the internal clock signal for sequentially processing the input data. The output interface operates in response to the external synchro signal for sequentially outputting the processed data in synchronization with the external synchro signal.

Claims

1. An integrated circuit device comprising:

an input interface operative in response to an external clock signal for sequentially receiving data in synchronization with a given external [synchro] synchronization signal;

a phase-locked loop (PLL) unit [including an internal clock source] operative in phase-locked manner according to the external [synchro] synchronization signal and the external clock signal for generating an internal clock signal which is faster than the external clock signal;

a processing unit operative in response to the internal clock signal for sequentially processing the received data; and

an output interface operative in response to the external clock signal and the external synchronization signal for sequentially transmitting the processed data in synchronization with the external synchronization signal and the external clock signal.

2. The integrated circuit device according to claim 1;

further comprising an internal clock source, wherein the internal clock source comprises a ring oscillator composed of a chain of complimentary metal-oxide semi-conducter device (CMOS) inverters.

3. The integrated circuit device according to claim 1, further including a buffer interposed between the processing unit and either of the input and output interfaces for absorbing jitter caused by frequency difference between the external and internal clock signals.

4. The integrated circuit device according to claim 1, wherein the PLL unit comprises an internal clock source oscillator controllable by a control voltage signal for generating the internal clock signal having a variable frequency, a divider for frequency-dividing the internal clock signal by a given rate, another divider operative in synchronization with the external synchronization signal for frequency-dividing the external clock signal by another given rate such that divided frequencies of the internal and external clock signals are comparable to each other, and a phase comparator for comparing phases of the frequency-divided internal and external clock signals with each other to thereby produce the control voltage signal effective to phase-lock an oscillating frequency of the internal clock source oscillator according to the external synchronization signal.

5. The integrated circuit device of claim 1, wherein an error signal is determined by comparing the internal clock signal divided by a predetermined frequency with the external clock signal divided by a second predetermined frequency, and wherein the error signal is used in the PLL unit to maintain a phase-locked relationship between the internal clock signal and the external synchronization signal.

6. The integrated circuit device of claim 5, wherein the error signal is supplied as an input to a voltage controlled oscillator.

7. The integrated circuit device of claim 1, wherein said input interface includes at least one section of first-in first-out (FIFO) memory for sequentially receiving data from the input interface and sequentially transmitting data to the processing unit.

8. The integrated circuit device of claim 1, wherein the processing unit performs a digital signal processing function on the received data.

9. The integrated circuit device of claim 1, wherein said output interface includes at least one section of first-in first-out (FIFO) memory for sequentially receiving data from the processing unit and sequentially transmitting data to the output interface.

10. A method of operating an integrated circuit, comprising the steps of:

providing an external synchronization signal to the integrated circuit;

generating an internal clock signal within the integrated circuit that is faster than an external clock signal, said internal clock signal being based on the external synchronization signal and the external clock signal;

operating the integrated circuit by the internal clock signal;

processing data inputted to the integrated circuit based on the internal clock signal; and

outputting the processed data based on the external synchronization signal and the external clock signal.

11. The method according to claim 10, wherein a phase-locked loop (PLL) circuit within the integrated circuit is used to generate the internal clock signal.

12. The method according to claim 11, wherein the step of generating the internal clock signal further includes the step of generating the internal clock signal by the PLL circuit based on the external synchronization signal and the external clock signal.

13. The method according to claim 10, further including the step of sequentially inputting data synchronized with the external synchronization signal.

14. The method according to claim 10, further including the step of sequentially outputting the processed data synchronized with the external synchronization signal.