Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems
First Claim
1. A graphics and video controller comprising:
- an interface for receiving words of pixel data, each said word associated with an address buffer;
circuitry for writing each said word of said pixel data received by said interface to a one of on-screen and off-screen memory areas of a frame buffer;
circuitry for selectively retrieving said words from said on-screen and off-screen areas;
a first pipeline for processing words of graphics data retrieved from said frame buffer; and
a second pipeline for processing words of video data retrieved from said frame buffer.
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Reexamination
Accused Products
Abstract
A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.
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Citations
47 Claims
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1. A graphics and video controller comprising:
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an interface for receiving words of pixel data, each said word associated with an address buffer; circuitry for writing each said word of said pixel data received by said interface to a one of on-screen and off-screen memory areas of a frame buffer; circuitry for selectively retrieving said words from said on-screen and off-screen areas; a first pipeline for processing words of graphics data retrieved from said frame buffer; and a second pipeline for processing words of video data retrieved from said frame buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A controller comprising:
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circuitry for writing selectively each word of received data into s selected one of on-screen and off-screen memory spaces of a frame buffer; a first port for receiving video and graphics data, a word of said data received with an address of said memory spaces directing said word to be processed as a word of video data or a word of graphics data; a second port for receiving real-time video data; circuitry for generating an address associated with a selected one of said memory spaces for a word of said real-time video data; circuitry for selectively retrieving said words of data from said on-screen and off-screen memory spaces as data is rastered for driving a display; a graphics backend pipeline for processing ones of said words of data representing graphics data retrieved from said frame buffer; a video backend pipeline for processing other ones of said words of data representing video data retrieved from said frame buffer, said circuitry for retrieving always rastering a stream of data from said frame buffer to said graphics backend pipeline and rastering video data to said video backend pipeline when a display raster scan reaches a display position of a window; and output selector circuitry for selecting for output between words of data output from said graphics backend pipeline and words of data output from said video backend pipeline. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A display system comprising:
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a first backend pipeline for processing data; a second backend pipeline for processing graphics data disposed in parallel to said first processing pipeline; a multi-format frame buffer memory having on-screen and off-screen areas each operable to simultaneously store data in graphics and video formats; a input port for receiving both graphics and video data, each word of said data associated with an address directing said word to be processed as either graphics or video data; circuitry for writing a word of said playback data into a selected one of said areas of said multi-format memory; memory control circuitry for controlling the transfer of data between said first backend pipeline and said frame buffer and between said second backend pipeline and said frame buffer; a display unit; and overlay control circuitry for selecting for output to said display unit between data provided by said first backend pipeline and data provided by said second backend pipeline. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A display data processing system comprising:
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circuitry for writing data into an on-screen space of a frame buffer; circuitry for writing data into an off-screen space of said frame buffer; a video pipeline for processing data output from a selected one of said on-screen and off-screen spaces comprising; a first first-in-first-out memory for receiving selected data from said selected space; a second first-in-first-out memory disposed in parallel to said first first-in-first-out memory for receiving other selected data from said selected space; and an interpolator for generating additional data by interpolating data output from said respective first and second first-in-first-out memories; a graphics pipeline disposed in parallel to said video pipeline for processing data output from a selected one of said on-screen and off-screen spaces; and an output selector for selecting between data output from said video pipeline and data output from said graphics pipeline. - View Dependent Claims (35, 36)
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37. A display controller comprising:
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circuitry for selectively retrieving data from an associated multi-format frame buffer for simultaneously snoring graphics and video data; a first pipeline for processing words of graphics data selectively retrieved from said frame buffer; and a second pipeline for processing words of video data selectively retrieved from said frame buffer. - View Dependent Claims (38, 39, 40, 41, 42)
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43. A display controller for interfacing a multi-format frame buffer and a display device, the multi-format frame buffer having on-screen and off-screen areas each for simultaneously storing both graphics and video pixel data, said display controller comprising:
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circuitry for selectively retrieving pixel data from a selected one of said on-screen and off-screen areas of said frame buffer; a graphics backend pipeline for processing graphics data retrieved from said selected one of said areas of said frame buffer; a video backend pipeline for processing video data retrieved from said selected one of said areas of said frame buffer; and an output selector for selectively passing to said display device data received from said graphics or video backend pipelines. - View Dependent Claims (44, 45, 46, 47)
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Specification