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Node loop port communication interface super core for fibre channel

  • US 5,598,541 A
  • Filed: 10/24/1994
  • Issued: 01/28/1997
  • Est. Priority Date: 10/24/1994
  • Status: Expired due to Term
First Claim
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1. A Super Core integrated system for use in a communication environment such as fibre channel for encoding and decoding data and implementing frame structures and byte sequences within a node port comprisingcore circuitry for encoding and decoding data and error checking said data,staging buffers connected with said core circuitry including Receive Buffer Logic and transmit buffer logic, said Receive Buffer Logic and said transmit buffer logic including buffers for frame headers and link frames and providing control to read and write from headers and link frames in buffers base on programmed steering,buffer status register files for storing status of header and link buffers in said Receive Buffer Logic and said write buffer logic,direct memory access control means for providing a data transfer interface to a local/host memory,an embedded processor for facilitating data transfers to and from local/host memory,a Receive Sequence State Machine coupled to said core circuitry, said staging buffers, said buffer status register files, said processor, and said direct memory access control means, said Receive Sequence State Machine controlling the transfer of data frames to memory including updating sequence and exchange information and generating interrupts to said processor when all data frames of a sequence are received, when termination of a sequence is received, when link control frames are received, and upon receipt of partial sequence data,a Transmit Sequence State Machine coupled to said core circuitry, said staging buffers and said buffer status register files, said processor and said direct memory access control means, said Transmit Sequence State Machine controlling transmission of data sequences and link frames from host memory to staging buffers, andan Exchange and Sequence Management Buffer Logic connected with said processor, said Receive Sequence State Machine, and said Transmit Sequence State Machine, said Exchange and Sequence Management Buffer Logic providing control of exchange and sequence status information and including storage buffers for exchange information and sequence information of data exchange to and from memory through said Receive sequence State Machine and said Transmit Sequence State Machine.

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