Node loop port communication interface super core for fibre channel

• US 5,598,541 A
• Filed: 10/24/1994
• Issued: 01/28/1997
• Est. Priority Date: 10/24/1994
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Malladi, Srinivasa R.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/329,032
• Time in Patent Office: 827 Days
• Field of Search: 370/59, 370/85.15, 370/94.1, 395/200.17, 395/200.21, 395/286, 395/185.02
• US Class Current: 710/106
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches

Abstract

A flexible architecture for the Super Core for implementing the FC-1 transmission protocol and the FC-2 signalling (framing) protocol in a 1.0625 Gbit/second Fibre Channel, which realizes 80 Mbytes/second sustained throughput. The architecture supports multiple, concurrent, open, and active exchanges and sequences with the use of an embedded control processor with all necessary time-critical functions performed in hardware and less critical performed by the embedded processor firmware.

Claims

1. A Super Core integrated system for use in a communication environment such as fibre channel for encoding and decoding data and implementing frame structures and byte sequences within a node port comprising

core circuitry for encoding and decoding data and error checking said data,

staging buffers connected with said core circuitry including Receive Buffer Logic and transmit buffer logic, said Receive Buffer Logic and said transmit buffer logic including buffers for frame headers and link frames and providing control to read and write from headers and link frames in buffers base on programmed steering,

buffer status register files for storing status of header and link buffers in said Receive Buffer Logic and said write buffer logic,

direct memory access control means for providing a data transfer interface to a local/host memory,

an embedded processor for facilitating data transfers to and from local/host memory,

a Receive Sequence State Machine coupled to said core circuitry, said staging buffers, said buffer status register files, said processor, and said direct memory access control means, said Receive Sequence State Machine controlling the transfer of data frames to memory including updating sequence and exchange information and generating interrupts to said processor when all data frames of a sequence are received, when termination of a sequence is received, when link control frames are received, and upon receipt of partial sequence data,

a Transmit Sequence State Machine coupled to said core circuitry, said staging buffers and said buffer status register files, said processor and said direct memory access control means, said Transmit Sequence State Machine controlling transmission of data sequences and link frames from host memory to staging buffers, and

an Exchange and Sequence Management Buffer Logic connected with said processor, said Receive Sequence State Machine, and said Transmit Sequence State Machine, said Exchange and Sequence Management Buffer Logic providing control of exchange and sequence status information and including storage buffers for exchange information and sequence information of data exchange to and from memory through said Receive sequence State Machine and said Transmit Sequence State Machine.

2. The Super Core integrated system as defined by claim 1 wherein said direct memory access control means includes a first direct memory access controller connected between said Receive Sequence State Machine and a local/host memory to provide a data transfer interface for received data frames and received link frames, and a second direct memory access controller connected between said Transmit Sequence State Machine and a local/host memory to provide a data transfer interface for transmit data frames and transmit link frames.

3. The Super Core integrated system as defined by claim 1 wherein said processor handles exceptional conditions, processes and generates primitive sequences, processes arbitration, controls said direct memory access control means in sending and receiving blocks of data, and performs all link control frame processing.

4. The Super Core integrated system as defined by claim 1 wherein said core circuitry includes

a decode word means for conversion of 10-bit data to 8-bit data with error checking, recognizing a comma character, constructing 32 bit parity protected words from half words or bytes, and providing decode error,

an encode word means for conversion of 8-bit data to 10-bit data, generating comma characters, and constructing half words or bytes from 32 bit parity protected words,

an arbitrated loop for performing loop initialization protocol and loop arbitration functions,

a receive unit for frame parsing, frame steering, error checking, primitive detection, and offset computation, and

a transmit unit for frame construction, CRC generation, and primitive generation.

5. The Super Core integrated system as defined by claim 1 wherein said Receive Sequence State Machine includes

a processor interface for generating interrupts,

a direct memory access controller interface for transferring data from staging buffers in said Receive Buffer Logic to local/host memory,

a buffer status register file interface,

an Exchange and Sequence Management Buffer Logic interface to access and update exchange and sequence status information,

a process acknowledgement unit for processing acknowledgements and updating exchange and sequence information, and

a control unit for all units of said Receive Sequence State Machine.

6. The Super Core integrated system as defined by claim 1 wherein said Transmit Sequence State Machine includes

a program DMA unit to program said direct memory access control means for the transmission of activated blocks, write an acknowledgement frame to said transmit buffer logic, read exchange and sequence status blocks, and to transfer data from local/host memory to staging buffers in said transmit buffer logic,

an Exchange and Sequence Management Buffer Logic interface for accessing and updating exchange and sequence status information of active and open exchanges and sequences, and to write information of active and open exchanges,

a buffer status register files interface for checking availability of header buffers and link buffers,

a generate acknowledgement unit for generating acknowledgements and updating exchange and sequence information,

a Transmit Sequence State Machine control unit for controlling other units including programming said direct memory access control means to write headers in response to availability of header buffers and link buffers, updating sequence and exchange information of transmitted frames, controlling sequence identification and exchange identification to Exchange and Sequence Management Buffer Logic interface for search and exchange information, and controlling said generate acknowledgement unit to transmit an acknowledgement frame and update exchange and sequence information, and

a processor interface for programming said Transmit Sequence State Machine to transmit a sequence of data, a single frame of data, and a link frame, generating interrupts to said processor under exceptional conditions, at the end of transmission of a frame sequence from local/host memory, at the end of an exchange, and when an exchange search or sequence search on Exchange and Sequence Management Buffer Logic fails.

7. The Super Core integrated system as defined by claim 1 wherein said Exchange and Sequence Management Buffer Logic includes

an exchange sequence interface pseudo cache including tags and data fields,

a pseudo cache control unit for acquiring a tag being searched, indicating cache hit success and failure when asked for exchange and sequence information, and providing read/write control signals to said P cache,

a Receive Sequence State Machine interface for providing a tag being searched by said Receive Sequence State Machine, and acquiring cache hit success and fail from P cache control and providing to said Receive Sequence State Machine, and

a Transmit Sequence State Machine interface for providing a tag being searched by said Transmit Sequence State Machine, and acquiring cache hit success and fail from P cache control and providing to said Transmit Sequence State Machine.

8. The Super Core integrated system as defined by claim 1 wherein said Receive Buffer Logic includes

Write Control Logic for receiving buffer write control and frame steering signals from said core circuitry,

first buffers for holding headers and entire link control frames, for a class 1 service,

second buffers for holding headers and entire link control frames for class 2/3 service,

a payload buffer for holding payloads of class 1, class 2, and class 3 frames, and

read control logic for reading from buffers.

9. The Super Core integrated system as defined by claim 1 wherein said transmit buffer logic includes

Write Control Logic for receiving buffer write control and frame steering from said Transmit Sequence State Machine,

first buffers for holding headers of a class 1 service,

second buffers for holding headers of a class 2/3 service,

third buffers for holding entire link frames to be transmitted,

a payload buffer for holding payloads of class 1, class 2, and class 3 frames, and

read control logic for reading from buffers.

10. The Super Core integrated system as defined by claim 1 wherein said buffer status register files includes multi-port register files for storing status of header and link buffers and interfacing with said processor, said Receive Buffer Logic, said Receive Sequence State Machine, said transmit buffer logic, said Transmit Sequence State Machine.

11. A Super Core integrated system for use in a fibre channel communication environment for encoding and decoding data and implementing frame structures and byte sequences within a node port comprising

a) core circuitry for encoding and decoding data and error checking said data, said core circuitry including

a decode word means for conversion of 10-bit data to 8-bit data with error checking, recognizing a comma character, constructing 32 bit parity protected words from half words and bytes, and providing decode error,

an encode word means for conversion of 8-bit data to 10-bit data, generating comma characters, and constructing half words and bytes from 32 bit parity protected words,

an arbitrated loop for performing loop initialization protocol and loop arbitration functions,

a receive unit for frame parsing, frame steering, error checking, primitive detection, and offset computation, and

a transmit unit for frame construction, CRC generation, and primitive generation,

b) staging buffers connected with said core circuitry including Receive Buffer Logic and transmit buffer logic, said Receive Buffer Logic and said transmit buffer logic including buffers for frame headers and link frames and providing control to read and write from headers and link frames in buffers based on programmed steering, said Receive Buffer Logic including,

Write Control Logic for receiving buffer write control and frame steering signals from said core circuitry,

first buffers for holding headers and entire link control frames, for a class 1 service,

second buffers for holding headers and entire link control frames for class 2/3 service,

a payload buffer for holding payloads of class 1, class 2, and class 3 frames, and

read control logic for reading from buffers, said transmit buffer logic including

Write Control Logic for receiving buffer write control and frame steering from said Transmit Sequence State Machine,

first buffers for holding headers of a class 1 service,

second buffers for holding headers of a class 2/3 service,

third buffers for holding entire link frames to be transmitted,

a payload buffer for holding payloads of class 1, class 2, and class 3 frames, and

read control logic for reading from buffers,

c) buffer status register files for storing status of header and link buffers in said Receive Buffer Logic and said write buffer logic, said buffer status register files including multi-port register files for storing status of header and link buffers and interfacing with said processor, said Receive Buffer Logic, said Receive Sequence State Machine, said transmit buffer logic, said Transmit Sequence State Machine,

d) direct memory access control means, including a first direct memory access controller connected between said Receive Sequence State Machine and a local memory to provide a data transfer interface for received data frames and received link frames, and a second direct memory access controller connected between said Transmit Sequence State Machine and a local memory to provide a data transfer interface for transmit data frames and transmit link frames,

e) an embedded processor, for handling exceptional conditions processes and generates primitive sequences, processes arbitration, controls said direct memory access control means in sending and receiving blocks of data, and performs all link control frame processing,

f) a Receive Sequence State Machine coupled to said core circuitry, said staging buffers, said buffer status register files, said processor, and said direct memory access control means, said Receive Sequence State Machine controlling the transfer of data frames to memory including updating sequence and exchange information and generating interrupts to said processor when all data frames of a sequence are received, when termination of a sequence is received, and when link control frames are received, said Receive Sequence State Machine including

a processor interface for generating interrupts,

a direct memory access controller interface for transferring data from staging buffers in said Receive Buffer Logic to memory,

a buffer status register file interface,

an Exchange and Sequence Management Buffer Logic interface to access and update exchange and sequence status information,

a process acknowledgement unit for processing acknowledgements and updating exchange and sequence information, and

a Control unit for all units of said Receive Sequence State Machine,

g) a Transmit Sequence State Machine coupled to said core circuitry, said staging buffers and said buffer status register files, said processor and said direct memory access control means, said Transmit Sequence State Machine controlling transmission of data sequences and link frames from memory to buffers, said Transmit Sequence State Machine including

a program DMA unit to program said direct memory access control means for the transmission of activated blocks, write an acknowledgement frame to said transmit buffer logic, read exchange and sequence status blocks, and to transfer data from local memory to staging buffers in said transmit buffer logic,

an Exchange and Sequence Management Buffer Logic interface for accessing and updating exchange and sequence status information of active and open exchanges and sequences, and to write information of active and open exchanges,

a buffer status register files interface for checking availability of header buffers and link buffers,

a generate acknowledgement unit for generating acknowledgements and updating exchange and sequence information,

a Transmit Sequence State Machine control unit for controlling other units including programming said direct memory access control means to write headers in response to availability of header buffers and link buffers, updating sequence and exchange information of transmitted frames, controlling Sequence identification and exchange identification to Exchange and Sequence Management Buffer Logic interface for search and exchange information, and controlling Said generate acknowledgement unit to transmit an acknowledgement frame and update exchange and sequence information, and

a processor interface for programming said Transmit Sequence State Machine to transmit a sequence of data, a single frame of data, and a link frame, generating interrupts to said processor under exceptional conditions, at the end of transmission of a frame sequence from local memory, at the end of an exchange, and when an exchange search or sequence search on Exchange and Sequence Management Buffer Logic fails, and

h) an Exchange and Sequence Management Buffer Logic connected with said processor, said Receive Sequence State Machine, and said Transmit Sequence State Machine, said Exchange and sequence Management Buffer Logic providing control of exchange and sequence status information and including storage buffers for exchange information and sequence information, said exchange and sequence information buffer logic including

an exchange sequence interface p cache including tags and data fields,

a P cache control unit for acquiring a tag being searched, indicating cache hit success and failure when asked for exchange and sequence information, and providing read/write control signals to said P cache,

a Receive Sequence State Machine interface for providing a tag being searched by said Receive Sequence State Machine, and acquiring cache hit success and fail from P cache control and providing to said Receive Sequence State Machine, and

a Transmit Sequence State Machine interface for providing a tag being searched by said Transmit Sequence State Machine, and acquiring cache hit success and fail from P cache control and providing to said Transmit Sequence State Machine.