Dual-architecture super-scalar pipeline

• US 5,598,546 A
• Filed: 08/31/1994
• Issued: 01/28/1997
• Est. Priority Date: 08/31/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Exponential Technology, Inc.
• Inventors: Blomgren, James S.
• Primary Examiner(s): Treat, William M.
• Assistant Examiner(s): Najjar, Saleh
• Application Number:
  US08/298,583
• Time in Patent Office: 881 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/209
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders

Abstract

A dual-instruction-set processor processes instructions from two or more instruction sets. The processor has several pipelines for processing different types of operations--Memory, ALU, and Branch operations. Instructions are decoded by RISC and CISC instruction decoders which generate control words for the pipelines. The control words are encoded by the operation to be performed by the pipelines, which can overlap for the instruction sets. A different format for the control word is used for each pipeline, but the format is the same for all instruction sets. Once the control words are generated and sent to the pipelines, an indication of the instruction set is no longer needed. Thus instructions from several instruction sets may be freely mixed in the pipelines, and there is no need to flush the pipelines when the instruction set is switched. Register operands are first converted to their RISC equivalents by the instruction decoders so that bypass and interlock logic may detect dependencies between instructions from any instruction set. Pipeline valid bits encode the order that instructions were in, allowing dependencies to exist within a group of instructions at the same stage in the pipelines. A dispatcher can decode and dispatch up to three instructions in a single clock cycle, although the third instruction dispatched can only be a simple branch. Compound instructions may require more than one pipeline for processing, and two or more control words are generated for these complex instructions, with one control word sent to each pipeline.

Claims

1. A central processing unit (CPU) for processing instructions from two separate instruction sets, the CPU comprising:

RISC instruction decode means for decoding instructions from a RISC instruction set, the RISC instruction set having a first encoding of operations;

CISC instruction decode means for decoding instructions from a CISC instruction set, the CISC instruction set having a second encoding of operations, the first encoding of operations substantially independent from the second encoding of operations;

instruction set indicating means for indicating an instruction set to be decoded, the instruction set indicating means having a RISC state indicating that the RISC instruction set be decoded, the instruction set indicating means having a CISC state indicating that the CISC instruction set be decoded;

select means, coupled to the RISC instruction decode means and the CISC instruction decode means, for outputting a control word, the control word generated from a decoding of an instruction from the RISC instruction set by the RISC instruction decode means when the instruction set indicating means is in the RISC state, the control word generated from a decoding of an instruction from the CISC instruction set by the CISC instruction decode means when the instruction set indicating means is in the CISC state, the control word having a third encoding of operations to control words, the third encoding of operations to control words being related to but substantially different from the first encoding and the second encoding; and

execute means, coupled to the select means and receiving the control word, for executing operations, the execute means executing an operation decoded by the RISC instruction decode means when the instruction set indicating means is in the RISC state, the execute means executing an operation decoded by the CISC instruction decode means when the instruction set indicating means is in the CISC state,

wherein RISC instructions and CISC instructions are directly decoded to the control word, the CISC instructions not being translated to RISC instructions,

whereby instructions from both the RISC instruction set and the CISC instruction set are decoded into control words which are executed by the CPU.

2. The CPU of claim 1 wherein the execute means comprises:

a plurality of pipelines, each pipeline in the plurality of pipelines comprising a sequence of stages, each pipeline for executing a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set, each pipeline responsive to a particular format of the control word.

3. The CPU of claim 2 wherein

the select means generates the control word and a secondary control word when a compound instruction is decoded, the compound instruction encoding two operations, a primary operation and a secondary operation, and wherein the plurality of pipelines comprises:

a first pipeline, receiving the control word, for executing the primary operation indicated by the control word; and

a second pipeline, receiving the secondary control word, for executing the secondary operation indicated by the secondary control word,

whereby compound instructions are decoded into two control words which are executed by two pipelines.

4. The CPU of claim 2 wherein the RISC instruction decode means and the CISC instruction decode means comprise a first decoder, the first decoder decoding a first instruction which encodes a first operation, the plurality of pipelines further comprising:

a first pipeline for executing a first subset of operations, the first subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set; and

a second pipeline for executing a second subset of operations, the second subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set;

the CPU further comprising;

a second decoder for decoding a second instruction which encodes a second operation, the second decoder having a RISC instruction decode means for decoding RISC instructions and a CISC instruction decode means for decoding CISC instructions, the second decoder outputting a second control word, the second control word encoding an operation of a RISC instruction when the instruction set indicating means is in the RISC state but the second control word encoding an operation of a CISC instruction when the instruction set indicating means is in the CISC state; and

dispatch means for allocating the plurality of pipelines, the dispatch means allocating the first pipeline to the first decoder if the first operation is an operation in the first subset of operations, the dispatch means allocating the second pipeline to the first decoder if the first operation is an operation in the second subset of operations,

the dispatch means further allocating the first pipeline to the second decoder if the second operation is an operation in the first subset of operations and the first operation is outside of the first subset of operations, the dispatch means allocating the second pipeline to the second decoder if the second operation is an operation in the second subset of operations and the first operation is outside of the second subset of operations,

whereby two RISC or CISC instructions are dispatched to the plurality of pipelines.

5. The CPU of claim 4 further comprising:

a pipeline valid array, loaded by the dispatch means, for indicating valid instructions in the plurality of pipelines, the pipeline valid array encoding if the first operation is in the first subset of operations, the second subset of operations, or not valid, the pipeline valid array further encoding if the second operation is in the first subset of operations, the second subset of operations, or not valid,

whereby validity and order of operations in the plurality of pipelines is encoded and stored in the pipeline valid array.

6. The CPU of claim 5 wherein the first subset of operations comprises arithmetic-logic-unit (ALU) operations, the CPU further comprising a floating point pipeline for processing floating point operations, the dispatch means allocating both the floating point pipeline and the first pipeline to a floating point instruction decoded by the first decoder.

7. The CPU of claim 4 wherein

the plurality of pipelines further comprises a third pipeline for executing a third subset of operations, the third subset of operations comprising operations encoded by the RISC instruction set and operations encoded by the CISC instruction set,

the dispatch means allocating the third pipeline to the first decoder if the first operation is an operation in the third subset of operations, the dispatch means allocating the third pipeline to the second decoder if the second operation is an operation in the third subset of operations and the first operation is outside of the third subset of operations.

8. The CPU of claim 7 further comprising

a third decoder for decoding a third instruction encoding a third operation, the third decoder having a RISC instruction decode means for decoding RISC instructions, the third decoder outputting a third control word encoding a RISC branch operation when the third instruction is a RISC branch instruction, the third decoder being disabled when the third instruction is not a RISC branch instruction;

and wherein

the dispatch means allocates the third pipeline to the third decoder if the third operation is a RISC branch operation and the first operation is outside of the third subset and the second operation is outside of the third subset,

whereby a third instruction is dispatched to the third pipeline if the third instruction is a RISC branch instruction.

9. The CPU of claim 8 wherein

the first subset of operations comprises arithmetic-logic-unit (ALU) operations, the first pipeline for executing ALU operations;

the second subset of operations comprises memory operations, the second pipeline for executing memory operations; and

the third subset of operations comprises branch operations, the third pipeline for executing branch operations.

10. The CPU of claim 2 wherein the RISC instruction decode means and the CISC instruction decode means comprise a first decoder, the first decoder decoding a first instruction which encodes a first operation, the plurality of pipelines further comprising:

a first pipeline for executing a first subset of operations, the first subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set; and

a second pipeline for executing a second subset of operations, the second subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set;

the CPU further comprising;

second instruction set indicating means for indicating an instruction set to be decoded for a second instruction, the second instruction set indicating means having a RISC state indicating that the RISC instruction set be decoded, the second instruction set indicating means having a CISC state indicating that the CISC instruction set be decoded;

a second decoder for decoding the second instruction which encodes a second operation, the second decoder having a RISC instruction decode means for decoding RISC instructions and a CISC instruction decode means for decoding CISC instructions, the second decoder outputting a second control word, the second control word encoding an operation of a RISC instruction when the second instruction set indicating means is in the RISC state but the second control word encoding an operation of a CISC instruction when the second instruction set indicating means is in the CISC state; and

dispatch means for allocating the plurality of pipelines, the dispatch means allocating the first pipeline to the first decoder if the first operation is in the first subset of operations, the dispatch means allocating the second pipeline to the first decoder if the first operation is in the second subset of operations,

the dispatch means further allocating the first pipeline to the second decoder if the second operation is an operation in the first subset of operations and the first operation is outside of the first subset of operations, the dispatch means allocating the second pipeline to the second decoder if the second operation is an operation in the second subset of operations and the first operation is outside of the second subset of operations,

whereby both a RISC and a CISC instruction are dispatched to the plurality of pipelines.

11. The CPU of claim 10 wherein

the second instruction set indicating means is coupled to the instruction set indicating means,

if the first operation is outside of a subset of instruction-set-switching operations, the second instruction set indicating means is in the RISC state when the instruction set indicating means is in the RISC state, the second instruction set indicating means is in the CISC state when the instruction set indicating means is in the CISC state;

if the first operation is in the subset of instruction-set-switching operations, the second instruction set indicating means switches to the RISC state when the instruction set indicating means is in the CISC state, the second instruction set indicating means switching to the CISC state when the instruction set indicating means is in the RISC state,

whereby the second decoder switches to decoding an alternate instruction set when an instruction-set-switching instruction is decoded by the first decoder.

12. The CPU of claim 11 wherein the first and second instructions are dispatched within a single clock period, whereby a CISC and a RISC instruction are dispatched during the single clock period.

13. The CPU of claim 1 further comprising:

field decode means, receiving RISC instructions from the RISC instruction set and receiving CISC instructions from the CISC instruction set, for decoding source and destination fields which indicate registers in the CPU, the field decode means coupled to the instruction set indicating means,

the field decode means outputting codes, including source codes and destination codes for registers accessible to the RISC instructions when the instruction set indicating means is in the RISC state, the field decode means converting codes for registers accessible to CISC instructions into codes for registers accessible to RISC instructions when the instruction set indicating means is in the CISC state,

whereby a single set of register codes is used by RISC instructions and CISC instructions.

14. The CPU of claim 13 further comprising

bypass and interlock control means, receiving the codes for registers from the field decode means, for bypassing a result from a prior instruction to a source for a current instruction when a destination code for the prior instruction matches a source code for the current instruction,

wherein the current instruction has a dependency to the prior instruction when the destination code for the prior instruction matches the source code for the current instruction, and wherein the prior instruction and the current instruction belong to different instruction sets,

whereby a dependency may be detected between instructions from different instruction sets.

15. The CPU of claim 4 wherein the first decoder further comprises

means for detecting a move immediate instruction, the move immediate instruction encoding a move immediate operation, both the first subset of operations and the second subset of operations including the move immediate operation, the first pipeline for executing the move immediate operation and the second pipeline for executing the move immediate operation;

and wherein if a move immediate instruction is detected by the means for detecting

the dispatch means allocates the first pipeline to the second decoder if the second operation is an operation in the first subset of operations, the dispatch means allocates the second pipeline to the second decoder if the second operation is an operation in the second subset of operations,

the dispatch means further allocates the first pipeline to the first decoder if the first operation is an operation in the first subset of operations and the second operation is outside of the first subset of operations, the dispatch means allocates the second pipeline to the first decoder if the first operation is an operation in the second subset of operations and the second operation is outside of the second subset of operations,

whereby the second instruction is dispatched to the plurality of pipelines before the first instruction is dispatched when a move immediate instruction is detected in the first decoder.

16. A microprocessor for processing instructions from two separate instruction sets, the microprocessor comprising:

CISC

RISC instruction decode means for decoding instructions from a RISC instruction set, the RISC instruction set having a first encoding of operations, the RISC instruction decode means generating a first control word encoding an operation decoded by the RISC instruction decode means;

CISC instruction decode means for decoding instructions from a CISC instruction set, the CISC instruction set having a second encoding of operations, the first encoding of operations substantially independent from the second encoding of operations, the CISC instruction decode means generating a second control word encoding an operation decoded by the CISC instruction decode means;

select means, coupled to the RISC instruction decode means and the CISC instruction decode means, for selecting either the first control word from the RISC instruction decode means or the second control word from the CISC instruction decode means;

instruction set indicating means for indicating an instruction set to be decoded, the instruction set indicating means having a first state indicating that the RISC instruction set be decoded, the instruction set indicating means having a second state indicating that the CISC instruction set be decoded;

the instruction set indicating means coupled to the select means, the select means selecting the first control word from the RISC instruction decode means when the instruction set indicating means is in the first state indicating that the RISC instruction set be decoded, the select means selecting the second control word from the CISC instruction decode means when the instruction set indicating means is in the second state indicating that the CISC instruction set be decoded;

the first control word and the second control word both having a third encoding of operations to control words, the third encoding of operations to control words being related to but substantially different from the first encoding and the second encoding; and

execute means, coupled to the select means and receiving first control words and second control words, for executing operations, the execute means executing the operation decoded by the RISC instruction decode means when the first control word is received from the select means, the execute means executing the operation decoded by the CISC instruction decode means when the second control word is received from the select means,

whereby instructions from both the RISC instruction set and the CISC instruction set are decoded into control words which are executed by the microprocessor.

17. The microprocessor of claim 16 wherein the execute means comprises:

a plurality of pipelines, each pipeline in the plurality of pipelines comprising a sequence of stages, each pipeline for executing a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set, each pipeline responsive to a particular format of control words.

18. A method for simultaneously processing instructions from a plurality of instruction sets in a processor having a plurality of pipelines, the method comprising:

decoding a RISC instruction in a RISC instruction decoder and determining an operation encoded by a first opcode in the RISC instruction using a first encoding of operations to opcodes for a RISC instruction set;

allocating at least one pipeline in the plurality of pipelines to the RISC instruction, the at least one pipeline having a functional unit for performing the operation encoded by the first opcode;

generating at least one control word for the RISC instruction, the at least one control word for indicating to the functional unit to perform the operation encoded by the first opcode;

transmitting the at least one control word to the at least one pipeline;

executing the operation encoded by the first opcode in the at least one pipeline;

decoding a CISC instruction in a CISC instruction decoder and determining an operation encoded by a second opcode in the CISC instruction using the first encoding of operations to opcodes for the RISC instruction set when the RISC instruction is outside of a subset of instructions that change an instruction set being processed, but determining the operation encoded by the second opcode in the CISC instruction using a second encoding of operations to opcodes for the CISC instruction set when the RISC instruction is within the subset of instructions that change the instruction set being processed;

allocating a second pipeline in the plurality of pipelines to the second instruction, the second pipeline having a second functional unit for performing the operation encoded by the second opcode, the second pipeline being a different pipeline than the at least one pipeline;

generating a second control word for the CISC instruction, the second control word for indicating to the second functional unit to perform the operation encoded by the second opcode;

transmitting the second control word to the second pipeline; and

executing the operation encoded by the second opcode in the second pipeline;

whereby instructions from a plurality of instruction sets are processed by a plurality of pipelines.

19. The method of claim 18 wherein

the at least one control word is transmitted to the at least one pipeline and the second control word is transmitted to the second pipeline during a single clock cycle,

whereby the RISC and CISC instruction are dispatched within the single clock cycle.

20. The method of claim 19 wherein

the first encoding of operations to opcodes for the RISC instruction set is substantially independent from the second encoding of operations to opcodes for the CISC instruction set.

21. The method of claim 20 wherein

the subset of instructions that change the instruction set being processed comprises a plurality of unsupported complex instructions in the RISC instruction set that are not decodable by the RISC instruction decoder.