Data processor for conditionally modifying extension bits in response to data processing instruction execution

• US 5,598,571 A
• Filed: 03/08/1995
• Issued: 01/28/1997
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/401,400
• Time in Patent Office: 692 Days
• Field of Search: 395/375, 395/800, 395/2.48, 395/21
• US Class Current: 712/9
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying each of the plurality of extension values during execution of the data processing instruction, wherein the

data processing instruction is one of a preliminary and a non-preliminary instruction,

the preliminary instruction modifying each of the plurality of extension values in response to a result of the data processing instruction, and

the non-preliminary instruction modifying each of the plurality of extension values to be in a default state,

the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction.

2. The data processor of claim 1 wherein the plurality of extension values comprises:

a first extension bit for indicating a status information value; and

a second extension bit for indicating a sign value corresponding to a source operand of the data processing instruction.

3. The data processor of claim 2 wherein the first extension bit and the second extension bit are negated when the data processing instruction is a non-preliminary instruction.

4. The data processor of claim 2 wherein the first extension bit and the second extension bit are modified in response to execution of the data processing instruction when the data processing instruction is a preliminary instruction.

5. The data processor of claim 1 wherein the non-preliminary instruction is a saturating instruction and the preliminary instruction is a non-saturating instruction, wherein:

a result of the data processing operation is replaced by one of an upper bound and a lower bound when an overflow value corresponding to the result is in an asserted state and the data processing instruction is the non-preliminary instruction; and

the result of the data processing operation is not replaced when the overflow value corresponding to the result is in the asserted state and the data processing instruction is the preliminary instruction.

6. The data processor of claim 1 wherein the data processing operation is one of an addition operation and a subtraction operation.

7. The data processor of claim 6 wherein the first extension bit is a carry value when the data processing operation is the addition operation and the first extension bit is a borrow value when the data processing operation is the subtraction operation.

8. The data processor of claim 1 wherein the data processing instruction generates the source operand, the source operand being based upon the second extension bit.

9. The data processor of claim 1 wherein the data processing operation is one of an increment operation and a decrement operation.

10. The data processor of claim 9 wherein the first extension bit is a carry value when the data processing operation is the increment operation and the first extension bit is a borrow value when the data processing operation is the decrement operation.

11. The data processor of claim 9 wherein the second extension bit is not used during execution of both the increment operation and the decrement operation.

12. The data processor of claim 1 wherein the data processing instruction has a destination operand and a source operand, the instruction execution means comparing the destination operand with the source operand in response to the data processing instruction.

13. The data processor of claim 12 wherein the plurality of extension values are selectively modified to indicate a comparative relationship between the destination operand and the source operand used during execution of the data processing operation.

14. The data processor of claim 13 wherein the plurality of extension bits indicates one of a following condition:

i) the destination operand is greater than the source operand;

ii) the destination operand is less than the source operand; and

iii) the destination operand is equal to the source operand.

15. The data processor of claim 14 wherein the plurality of extension bits is placed in a default state during execution of the data processing operation.

16. The data processor of claim 1 wherein the data processing instruction enables the instruction execution means to execute a left shift operation using a source operand of the data processing instruction.

17. The data processor of claim 16 wherein a first one of the plurality of extension values is shifted into a least significant bit of the source operand.

18. The data processor of claim 1 wherein the data processing instruction enables the instruction execution means to execute a right shift operation using a source operand of the data processing instruction.

19. The data processor of claim 18 wherein the plurality of extension values comprises:

a first extension bit for indicating a shift data value; and

a second extension bit for indicating a first byte of source operand.

20. The data processor of claim 19 wherein a least significant bit of a previous significant byte of the source operand is shifted and stored in the first extension bit as the shift data value when the second extension bit is asserted.

21. The data processor of claim 19 wherein a sign value is shifted into a most significant bit of a first byte of the source operand when the second extension bit is negated.

22. The data processor of claim 1 wherein the data processing instruction enables the instruction execution means to execute a negation operation.

23. The data processor of claim 22 wherein a first one of the plurality of extension bits indicates when a borrow is generated during execution of the negation operation.

24. The data processor of claim 22 wherein the plurality of extension bits are placed in a default state during execution of the negation operation.

25. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying each of the plurality of extension values during execution of the data processing instruction, wherein the data processing instruction is one of a preliminary and a non-preliminary instruction,

the preliminary instruction modifying each of the plurality of extension values in response to a result of the data processing instruction, and

the non-preliminary instruction modifying each of the plurality of extension values to be in a default state,

wherein the non-preliminary instruction is a saturating instruction and the preliminary instruction is a non-saturating instruction, wherein;

a result of the data processing operation is replaced by one of an upper bound and a lower bound when an overflow value corresponding to the result is in an asserted state and the data processing instruction is the non-preliminary instruction, and

the result of the data processing operation is not replaced when the overflow value corresponding to the result is in the asserted state and the data processing instruction is the preliminary instruction,

the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction.

26. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, wherein the plurality of extension values comprises;

a first extension bit for indicating a status information value, and

a second extension bit for indicating a sign value corresponding to a source operand of the data processing instruction,

each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally negating the first extension bit and the second extension bit during execution of the data processing instruction when the data processing instruction is a non preliminary instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction.

27. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, wherein the plurality of extension values comprises;

a first extension bit for indicating a status information value, and

a second extension bit for indicating a sign value corresponding to a source operand of the data processing instruction,

each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying the first extension bit and the second extension bit during execution of the data processing instruction when the data processing instruction is a preliminary instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction.

28. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

storage means for storing a first extension bit and a second extension bit, each of the first and second extension bits being used during execution of the data processing operation;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction and being coupled to the storage means for communicating each of the first and second extension bits, wherein the data processing instruction generates the source operand and the source operand is based upon the second extension bit; and

modification means for conditionally modifying the first and second extension bits during execution of the data processing instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction.

29. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying each of the plurality of extension values during execution of the data processing instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction,

wherein the data processing instruction enables the instruction execution means to execute a left shift operation using a source operand of the data processing instruction and wherein a first one of the plurality of extension values is shifted into a least significant bit of the source operand.

30. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying each of the plurality of extension values during execution of the data processing instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction,

wherein the data processing instruction enables the instruction execution means to execute a right shift operation using a source operand of the data processing instruction, and

wherein the plurality of extension values comprises;

a first extension bit for indicating a shift data value; and

a second extension bit for indicating a first byte of source operand.

31. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

storage means for storing a plurality of extension values, each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying each of the plurality of extension values during execution of the data processing instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction,

wherein the data processing instruction enables the instruction execution means to execute a negation operation and a first one of the plurality of extension bits indicates when a borrow is generated during execution of the negation operation.

32. A data processor, comprising:

an instruction storage circuit for storing a data processing instruction;

instruction execution means for executing a data processing operation in response to the data processing instruction, the instruction execution means being coupled to the instruction storage circuit for receiving the data processing instruction;

.

storage means for storing a plurality of extension values, each of the plurality of extension values being used during execution of the data processing operation, the storage means being coupled to the instruction execution means for communicating each of the plurality of extension values; and

modification means for conditionally modifying each of the plurality of extension values during execution of the data processing instruction, the modification means being coupled to the storage means for communicating each of the plurality of extension values being conditionally modified in response to the data processing instruction,

wherein the data processing instruction enables the instruction execution means to execute a negation operation and wherein the plurality of extension bits are placed in a default state during execution of the negation operation.