Vertically integrated sensor structure and method

• US 5,600,071 A
• Filed: 07/22/1996
• Issued: 02/04/1997
• Est. Priority Date: 09/05/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sooriakumar, K., Chan, Wendy K., Monk, David J., Goldman, Kenneth G.
• Primary Examiner(s): Chilcot, Richard
• Assistant Examiner(s): Oen, William L.
• Application Number:
  US08/684,723
• Time in Patent Office: 197 Days
• Field of Search: 73/720, 73/721, 73/726, 73/727, 338/4, 338/5, 338/42
• US Class Current: 73/721
• CPC Class Codes: G01L 19/0084 to the outside of the housing other details about the housing see G01L19/14
• CPC Class Codes: G01L 19/0627 Protection against aggressive medium in general
• CPC Class Codes: G01L 19/143 Two part housings
• CPC Class Codes: G01L 19/147 Details about the mounting of the sensor to support or covering means
• CPC Class Codes: G01L 19/148 Details about the circuit board integration, e.g. integrated with the diaphragm surface or encapsulation
• CPC Class Codes: G01L 9/0055 bonded on a diaphragm
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A vertically integrated sensor structure (60) includes a base substrate (71) and a cap substrate (72) bonded to the base substrate (71). The base substrate (71) includes a transducer (78) for sensing an environmental condition. The cap substrate (72) includes electronic devices (92) formed on one surface to process output signals from the transducer (78). The sensor structure (60) provides an integrated structure that isolates sensitive components from harsh environments.

Claims

1. A vertically integrated sensor device comprising:

a base substrate having a first major surface, a second major surface opposite the first major surface, and a cavity extending from the second major surface to form a diaphragm, and wherein the base substrate comprises a semiconductor material;

a transducer formed on the diaphragm;

a cap substrate having a third major surface and a fourth major surface opposite the third major surface, wherein the third major surface is connected to the first major surface to provide a hermetically sealed chamber, and wherein the cap substrate comprises a semiconductor material; and

an electronic device formed on the fourth major surface, wherein the electronic device is electrically coupled to the transducer.

2. The device of claim 1 wherein the transducer comprises a piezoresistive element.

3. The device of claim 1 wherein the electronic device comprises an active device.

4. The device of claim 1 wherein the electronic device comprises a passive device.

5. The device of claim 1 wherein the electronic device is coupled to the transducer with a wire bond.

6. The device of claim 1 wherein the third major surface is bonded to the first major surface with a glass frit.

7. The device of claim 1 wherein the device forms a media compatible absolute pressure sensor.

8. A media compatible vertically integrated absolute pressure sensor structure comprising:

a first substrate comprising a semiconductor material and having a first cavity extending from a first surface to form a diaphragm;

a transducer formed on a second surface of the first substrate, the transducer providing an output signal when the first cavity is exposed to an environmental condition;

a second substrate comprising a semiconductor material and having a third surface and a fourth surface opposite the third surface, wherein the third surface is attached to the second surface such that a sealed chamber is formed above the diaphragm;

an integrated circuit device formed on the fourth surface, wherein the integrated circuit device is coupled to the first substrate for receiving the output signal from the transducer; and

a chip carrier having a pressure port, wherein the first substrate is coupled to the chip carrier such that the first cavity is in a spaced relationship with the pressure port.

9. The structure of claim 8 further comprising a second cavity formed in the second substrate, wherein the second cavity extends from the third surface.

10. The structure of claim 8 wherein the integrated circuit device includes an adjustable resistor.

11. The structure of claim 8 wherein the second substrate includes a beveled edge.

12. The structure of claim 8 wherein the chip carrier further includes conductive leads and wherein one of the first substrate and the second substrate are coupled to the conductive leads.

13. The structure of claim 12 wherein one of the first substrate and the second substrate are coupled to the conductive leads with a wire bond.

14. The structure of claim 8 wherein the third surface is attached to the second surface with a glass frit.

15. The structure of claim 8 further comprising a protective gel, wherein the protective gel covers the integrated circuit device.

16. A method for forming a vertically integrated sensor device comprising the steps of:

forming a first cavity in a base substrate, wherein the base substrate includes a first major surface and a second major surface, and wherein the first cavity extends from the first major surface to provide a diaphragm, and wherein the base substrate is comprised of a semiconductor material;

forming a transducer on the diaphragm;

forming an electronic device on a cap substrate, wherein the cap substrate includes a third major surface and a fourth major surface, wherein the electronic device is formed on the fourth major surface, and wherein the cap substrate is comprised of a semiconductor material;

attaching the cap substrate to the base substrate to provide a hermetically sealed chamber above the transducer;

attaching the base substrate to a chip carrier, wherein the chip carrier includes an opening, and wherein the first cavity is in a spaced relationship with the opening; and

coupling the transducer to the electronic device.

17. The method of claim 16 wherein the step of forming the electronic device includes forming a passive device.

18. The method of claim 16 wherein the step of forming the electronic device includes forming an adjustable resistor.

19. The method of claim 18 further comprising the step of adjusting the adjustable resistor after the step of attaching the base substrate to the chip carrier.

20. The method of claim 16 wherein the step of forming the electronic device includes forming an active device.

21. The method of claim 16 wherein the step of attaching the cap substrate to the base substrate includes attaching the cap substrate to the base substrate with a glass frit.

22. The method of claim 16 wherein the step of coupling the transducer to the electronic device includes coupling the transducer to the electronic device with a wire bond.

23. The method of claim 16 further comprising the steps of:

forming a second cavity in the cap substrate; and

forming a tapered edge on the cap substrate after the step of forming the electronic device and before the step of attaching the cap substrate to the base substrate.