Dynamically balanced fully differential circuit for use with a battery monitoring circuit

• US 5,600,247 A
• Filed: 08/17/1994
• Issued: 02/04/1997
• Est. Priority Date: 07/08/1992
• Status: Expired due to Term

• Current Assignee: Benchmarq Microelectronics, Inc. (Texas Instruments, Inc.)
• Original Assignee: Benchmarq Microelectronics, Inc. (Texas Instruments, Inc.)
• Inventors: Matthews, Wallace E.
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US08/291,688
• Time in Patent Office: 902 Days
• Field of Search: 324/426, 324/427, 324/428, 324/431, 324/433, 324/436, 320/48, 340/636
• US Class Current: 324/426
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H02J 7/00036 Charger exchanging data with battery
• CPC Class Codes: H02J 7/00047 with provisions for charging different types of batteries
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being provided to the battery or being extracted from the battery. The voltage across the sensor resistor (50) is sensed by a voltage/frequency converter (52). The voltage/frequency converter (52) is a differential structure comprised of two integrator structures (102) and (104) that are operable to utilize a switched capacitor configuration to drive comparators on the output thereof. Each of the integrator structures (102) and (104) has associated therewith passive elements and active elements. The integrators (102) and (104) have associated therewith integration capacitors (147) and (149). Additionally, there are two operational amplifiers (143) and (145) that provide the active components of each of the integrators (102) and (104). The various switched capacitor circuits (161) and (163) associated with the amplifiers (143) and (145) are provided to provide the integration operation. Both the amplifiers (143) and (145) and their associated switched capacitor circuits (161) and (163) are dynamically balanced such that they are switched between integrator (102) and integrator (104) on a periodic basis. This therefore allows the errors between the active and passive elements to be switched between the two integrators (102) and (104) such that no accumulative error occurs.

Claims

1. A battery monitoring circuit for monitoring current with a current monitor through a sense resistor disposed in series with one terminal of the battery by detecting the voltage across the sense resistor in order to determine the current through the battery terminal, the current monitor comprising:

a voltage-to-frequency converter for converting the voltage across the sense resistor to a primary pulse stream, the rate of said primary pulse stream corresponding to the voltage across the sense resistor;

a circuit for determining the current through the battery terminal, the current being a function of the rate of said primary pulse stream; and

said voltage-to-frequency converter having a differential structure associated therewith, said differential structure comprising;

a first differential leg having first passive switching elements and first active elements associated therewith for receiving as an input voltage the voltage that is across the sense resistor and processing the input voltage therethrough with said first passive switching elements and said first active elements in a first predetermined manner and outputting a first differential signal,

a second differential leg substantially identical to said first differential leg and having second passive switching elements and second active elements associated therewith for receiving as an input voltage the voltage across the sense resistor and processing the input voltage therethrough with said second passive switching elements and said second active elements in a second predetermined manner and outputting a second differential signal, said second differential signal being substantially similar to said first differential signal and of an opposite polarity with differences between said first and second differential signals resulting from differences between said first and second passive switching elements and said first and second active elements in said first and second differential legs, respectively, wherein positive transitions in said first differential signal will correspond to negative transitions in said second differential signal, such that said first and second differential signals comprise a differential output,

a multiplex circuit for periodically switching select portions of said first and second passive switching elements and said first and second active elements between said first and second differential legs to compensate for said differences between said first and second passive switching elements and said first and second active elements in said first and second differential legs, and

a pulse generation system for generating a first differential pulse stream having a pulse rate that is a function of said first differential signal and a second differential pulse stream having a pulse rate that is a function of said second differential signal and a summing circuit for summing said first and second differential pulse streams to provide said primary pulse stream.

2. The monitoring circuit of claim 1, wherein:

each of said first and second differential legs having associated therewith first and second switched capacitor integrators, respectively, that each provide an integrated voltage on the output of the respective one of said first and second switched capacitor integrators that is a function of the input voltage input thereto, the input voltage applied thereto being the voltage across the sense resistor;

said first switched capacitor integrator having a first integrator feedback capacitor associated therewith that comprises a portion of said first passive switching elements and first switched control signals;

said second switched capacitor integrator having a second integrator feedback capacitor associated therewith that comprises a portion of said second passive switching elements and second switched control signals;

a first switchable amplifier with an associated switched capacitor input structure which, when said first switchable amplifier has said first or second integrator feedback capacitor connected between the input and output thereof and said associated switched capacitor input structure controlled by said first or second switched control signals, will form said first or second switched capacitor integrator;

a second switchable amplifier with an associated switched capacitor input structure which, when said second switchable amplifier has said first or second integrator feedback capacitor connected between the input and output thereof and said associated switched capacitor structure controlled by said first or second switched control signals, will form said first or second switched capacitor integrator;

said first switchable amplifier comprising the select portion of said first active elements and said second switchable amplifier comprising the select portion of said second active elements and said associated switched capacitor input structures comprising the select portion of said first and second passive switching elements; and

said multiplex circuit operable to alternately switch said first and second switchable amplifiers between said first and second differential legs and said first and second integrator feedback capacitors.