Integrated circuit facilitating simultaneous programming of multiple antifuses

• US 5,600,262 A
• Filed: 10/11/1995
• Issued: 02/04/1997
• Est. Priority Date: 12/01/1994
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Kolze, Paige A.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/540,726
• Time in Patent Office: 482 Days
• Field of Search: 326/38, 326/44, 327/525, 437/922, 437/170, 437/172, 365/96
• US Class Current: 326/38
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

To facilitate the simultaneous programming of multiple antifuses on an integrated circuit, a first current path is established from a first programming terminal (VPP1) of a programmable logic device through a first antifuse to be programmed and a second current path is established from a second programming terminal (VPP2) of the programmable logic device through a second antifuse to be programmed. By supplying the programming current for programming the first antifuse from a different terminal than the programming current for programming the second antifuse, the two antifuses can be programmed simultaneously with an adequate amount of programming current being supplied to each antifuse. A programming current multiplexer circuit is disclosed for selectively coupling either a first programming voltage (VPP1) terminal, a second programming voltage (VPP2), or a ground terminal (GND) to a programming bus and/or to an antifuse to be programmed. The first and second current paths can be established using multiple such programming current multiplexer circuits.

Claims

1. An integrated circuit, comprising:

a first string;

a second string;

a third string;

a fourth string, each of said strings comprising;

a first conductor, a second conductor, an antifuse, and a pass transistor, said pass transistor being controllable to couple said first and second conductors together, said antifuse being disposed to couple said first and second conductors together if said antifuse is programmed, said first and second conductors extending in the same direction and being roughly collinear with one another, wherein said first conductors of said first, second, third and fourth strings are disposed to be parallel with one another;

a first control conductor extending in a direction substantially perpendicular to the direction said first and second conductors of each of said strings extend, said first control conductor being coupled to the gates of the pass transistors of said first and second strings;

a second control conductor roughly collinear with said first control conductor, said second control conductor being coupled to the gates of the pass transistors of said third and fourth strings;

a first programming bus extending in said direction said first control conductor extends, said first programming bus coupling said first and second strings together; and

a second programming bus roughly collinear with said first programming bus, said second programming bus coupling said third and fourth strings together.

2. The integrated circuit of claim 1, wherein the pass transistor of a string is directly connected to the first and second conductors of said string.

3. The integrated circuit of claim 1, wherein said second programming bus is collinear with said first programming bus.

4. The integrated circuit of claim 1, wherein the first programming bus is coupled to the first string via a first programming disable transistor, wherein the first programming bus is coupled to the second string via a second programming disable transistor, wherein the second programming bus is coupled to the third string via a third programming disable transistor, and wherein the second programming bus is coupled to the fourth string via a fourth programming disable transistor.

5. The integrated circuit of claim 1, further comprising:

a first programming current multiplexer coupled to said first programming bus; and

a second programming current multiplexer coupled to said second programming bus, wherein a first programming current flows through said first programming current multiplexer, through said first programming bus, and through an antifuse of said first string to program said antifuse of said first string, and wherein a second programming current flows through said second programming current multiplexer, through said second programming bus, and through an antifuse of said third string to program said antifuse of said third string, said antifuse of said first string and said antifuse of said third string being programmed simultaneously.