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Apparatus for a programmable CML to CMOS translator for power/speed adjustment

  • US 5,600,267 A
  • Filed: 11/28/1995
  • Issued: 02/04/1997
  • Est. Priority Date: 06/24/1994
  • Status: Expired due to Term
First Claim
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1. A translating circuit with a programmable power down option for translating a signal from a CML voltage level to a TTL voltage level, said translating circuit comprising:

  • a first amplifier circuit for amplifying said signal;

    a second amplifier circuit for amplifying said signal,said second amplifier circuit being coupled in parallel to said first amplifier circuit such that an input of said first amplifier circuit and an input of said second amplifier circuit are coupled to an input of said translating circuit;

    a programmable circuit liar controlling said first amplifier circuit and coupled to said first amplifier, said programmable circuit shutting down said first amplifier circuit in a power-down mode without shutting down said second amplifier circuit, wherein in said power-down mode, said second amplifier circuit responds to said signal independently of said first amplifier circuit; and

    a third amplifier circuit for translating said signal to a TTL voltage level, said third amplifier circuit having an input coupled to an output of said first amplifier circuit and an output of said second amplifier circuit, such that said third amplifier circuit being coupled in series with said first amplifier circuit and said second amplifier circuit, said third amplifier circuit having an output coupled to an output of said translating circuit.

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