Apparatus for a programmable CML to CMOS translator for power/speed adjustment
First Claim
1. A translating circuit with a programmable power down option for translating a signal from a CML voltage level to a TTL voltage level, said translating circuit comprising:
- a first amplifier circuit for amplifying said signal;
a second amplifier circuit for amplifying said signal,said second amplifier circuit being coupled in parallel to said first amplifier circuit such that an input of said first amplifier circuit and an input of said second amplifier circuit are coupled to an input of said translating circuit;
a programmable circuit liar controlling said first amplifier circuit and coupled to said first amplifier, said programmable circuit shutting down said first amplifier circuit in a power-down mode without shutting down said second amplifier circuit, wherein in said power-down mode, said second amplifier circuit responds to said signal independently of said first amplifier circuit; and
a third amplifier circuit for translating said signal to a TTL voltage level, said third amplifier circuit having an input coupled to an output of said first amplifier circuit and an output of said second amplifier circuit, such that said third amplifier circuit being coupled in series with said first amplifier circuit and said second amplifier circuit, said third amplifier circuit having an output coupled to an output of said translating circuit.
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Accused Products
Abstract
A CMOS circuit is disclosed for translating a signal from CML to CMOS logic voltage levels. The CMOS circuit includes two amplifier circuits coupled in parallel. The first amplifier circuit comprises of a programmable circuit and a CMOS inverter such that the CMOS inverter can be programmed "on" or "off" by the programmable circuit. The programmable circuit includes a programmable element which may be implemented using a fuse or floating gate technology. The second amplifying circuit comprises of a CMOS inverter. When the CMOS inverter in the first amplifier circuit is powered "on", the CMOS circuit is operating in a full power mode at high speed with both CMOS inverters operating. When the CMOS inverter in the first amplifier circuit is powered "off", the CMOS circuit is operating in a low power mode at a slower speed with only one CMOS inverter operating. During the full power and low power modes of operation, the translator circuit converts the CML circuit output signal, which has a full rail-to-rail output swing of about 1 volt, to CMOS compatible voltage levels, which is required to drive a TTL level output circuit.
90 Citations
26 Claims
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1. A translating circuit with a programmable power down option for translating a signal from a CML voltage level to a TTL voltage level, said translating circuit comprising:
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a first amplifier circuit for amplifying said signal; a second amplifier circuit for amplifying said signal, said second amplifier circuit being coupled in parallel to said first amplifier circuit such that an input of said first amplifier circuit and an input of said second amplifier circuit are coupled to an input of said translating circuit; a programmable circuit liar controlling said first amplifier circuit and coupled to said first amplifier, said programmable circuit shutting down said first amplifier circuit in a power-down mode without shutting down said second amplifier circuit, wherein in said power-down mode, said second amplifier circuit responds to said signal independently of said first amplifier circuit; and a third amplifier circuit for translating said signal to a TTL voltage level, said third amplifier circuit having an input coupled to an output of said first amplifier circuit and an output of said second amplifier circuit, such that said third amplifier circuit being coupled in series with said first amplifier circuit and said second amplifier circuit, said third amplifier circuit having an output coupled to an output of said translating circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A translating circuit with a programmable power down option for translating a signal from a CML voltage level to a TTL voltage level, said translating circuit comprising:
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a first translator circuit for translating said signal; a second translator circuit for translating said signal, said second translator circuit being coupled in parallel to said first translator circuit such than an input of said first translator circuit and an input of said second translator circuit are coupled to an input of said translating circuit; a programmable circuit for controlling said first translator circuit and coupled to said first translator circuit, said programmable circuit shutting down said first translator circuit in a power-down mode without shutting down said second translator circuit, wherein in said power-down mode, said second translator circuit responds to said signal independently of said first translator circuit; and a third translator circuit, said third translator circuit for translating said signal to a TTL voltage level, said third translator circuit being coupled in series with said first translator circuit and said second translator circuit, such that an output of said first translator circuit and an output of said second translator circuit ate coupled to an input of said third translator circuit, said third translator circuit having an output coupled to an output of said translating circuit. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification