Logarithm/inverse-logarithm converter utilizing linear interpolation and method of using same

• US 5,600,581 A
• Filed: 02/22/1995
• Issued: 02/04/1997
• Est. Priority Date: 02/22/1995
• Status: Expired due to Fees

• Current Assignee: Torsal Technology Group Limited LLC (Intellectual Ventures LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Smith, Stephen L., Dworkin, James D., Giangarra, Philip B.
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US08/391,880
• Time in Patent Office: 713 Days
• Field of Search: 364/722, 364/748, 364/748.5, 364/715.03, 364/736, 341/75
• US Class Current: 708/277
• CPC Class Codes: G06F 1/0307 Logarithmic or exponential functions G06F1/0314, G06F1/035 take precedence
• CPC Class Codes: H03M 7/50 Conversion to or from non-linear codes, e.g. companding

Abstract

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory, a multiplier, and an adder. The memory stores a plurality of pre-computed values which are used in an interpolation to estimate a logarithmic or inverse-logarithmic function over a domain of input signals.

Claims

1. A method for generating a log signal, which method comprises the following steps:

receiving a digital input signal having a first bit slice representing a plurality of most significant bits and a second bit slice representing a plurality of least significant bits;

retrieving from a memory a neighboring log value and a delta value corresponding to the first bit slice;

multiplying the second bit slice by the delta value to produce a term value;

generating a correction factor that represents the term value divided by an interval value; and

summing the correction factor and the neighboring log value to produce the log signal.

2. The method of claim 1, further comprising the following steps:

selecting a domain of input signals;

selecting a plurality of base points within the domain;

computing a respective neighboring log value for each of the plurality of base points, whereby producing a plurality of neighboring log values;

computing a plurality of delta values, wherein each of the plurality of delta values is equal to the difference between neighboring log values of adjacent base points; and

storing the plurality of neighboring log values and the plurality of delta values in the memory.

3. The method of claim 2, wherein the step of storing includes locating a neighboring log value and a delta value which correspond to a same input signal at a common address in the memory.

4. A logarithm converter, which comprises:

a memory for storing a plurality of neighboring log values and a plurality of delta values, the memory providing as output a neighboring log value and a delta value which correspond to a first bit slice of a digital input signal;

a multiplier for multiplying a second bit slice of the digital input signal by the delta value to produce a first term;

means for generating a correction factor that represents the first term divided by an interval value; and

an adder for summing the correction factor and the neighboring log value to produce the log signal.

5. The logarithm converter of claim 4, wherein the generating means includes:

a data path connecting a most significant portion of the multiplier output to a least significant portion of an adder input, whereby providing at the adder input the correction factor representing the first term divided by a power of two.

6. The logarithm converter of claim 4, wherein the pluralities of neighboring log values and delta values are pre-computed for a plurality base point values within a pre-selected domain of input signals.

7. The logarithm converter of claim 6, wherein ones of the neighboring log values and delta values corresponding to a same base point are located at a common address in the memory.

8. A logarithm converter for generating a log signal in response to a digital input signal, the logarithm converter comprising:

a memory for storing a plurality of neighboring log values and a plurality of delta values, the memory providing as output a neighboring log value and a delta value which correspond to a first bit slice of the input signal;

a multiplier for multiplying a second bit slice of the input signal by the delta value to produce a correction factor representing a first term divided by an interval value; and

an adder for summing the correction factor and the neighboring log value to produce the log signal.

9. The logarithm converter of claim 8, wherein the pluralities of neighboring log values and delta values are pre-computed for a plurality base point values within a pre-selected domain of input signals.

10. The logarithm converter of claim 9, wherein ones of the neighboring log values and delta values corresponding to a same base point are located at a common address in the memory.

11. A computing device, which comprises:

a processing unit for executing a computer operation which utilizes a log signal;

a computer memory for storing a computer program which includes the computer operation;

a bus for connecting the processing unit and the computer memory; and

a logarithm converter which receives a digital input signal and includes;

a memory for storing a plurality of neighboring log values and a plurality of delta values, the memory providing as output a neighboring log value and a delta value which correspond to a first bit slice of the digital input signal;

a multiplier for multiplying a second bit slice of the digital input signal by the delta value to produce a correction factor representing a first term divided by an interval value; and

an adder for summing the correction factor and the neighboring log value to produce the log signal.

12. The computing device of claim 11, wherein the pluralities of neighboring log values and delta values are pre-computed for a plurality base point values within a pre-selected domain of input signals.

13. The computing device of claim 12, wherein ones of the neighboring log values and delta values corresponding to a same base point are located at a common address in the memory.

14. A method for generating an inverse-log signal, which method comprises the following steps:

receiving a digital input signal having a first bit slice representing a plurality of most significant bits and a second bit slice representing a plurality of least significant bits;

retrieving from a memory a neighboring inverse-log value and a delta value corresponding to the first bit slice;

multiplying the second bit slice by the delta value to produce a term value;

generating a correction factor that represents the term value divided by an interval value; and

summing the correction factor and the neighboring log value to produce the inverse-log signal.

15. The method of claim 14, further comprising the following steps:

selecting a domain of input signals;

selecting a plurality of base points within the domain;

computing a respective neighboring inverse-log value for each of the plurality of base points, whereby producing a plurality of neighboring inverse-log values;

computing a plurality of delta values, wherein each of the plurality of delta values is equal to the difference between neighboring inverse-log values of adjacent base points; and

storing the plurality of neighboring inverse-log values and the plurality of delta values in the memory.

16. The method of claim 15, wherein the step of storing includes locating a neighboring inverse-log value and a delta value which correspond to a same input signal at a common address in the memory.

17. An inverse-logarithm converter, which comprises:

a memory for storing a plurality of neighboring inverse-log values and a plurality of delta values, the memory providing as output a neighboring inverse-log value and a delta value which correspond to a first bit slice of a digital input signal;

a multiplier for multiplying a second bit slice of the digital input signal by the delta value to produce a first term;

means for generating a correction factor that represents the first term divided by an interval value; and

an adder for summing the correction factor and the neighboring inverse-log value to produce the inverse-log signal.

18. The inverse-logarithm converter of claim 17, wherein the generating means includes:

a data path connecting a most significant portion of the multiplier output to a least significant portion of an adder input, whereby providing at the adder input the correction factor representing the first term divided by a power of two.

19. The inverse-logarithm converter of claim 17, wherein the pluralities of neighboring inverse-log values and delta values are pre-computed for a plurality of base point values within a pre-selected domain of input signals.

20. The inverse-logarithm converter of claim 19, wherein ones of the neighboring log values and delta values corresponding to a same base point are located at a common address in the memory.

21. A inverse-logarithm converter for generating a inverse-log signal in response to a digital input signal, the inverse-logarithm converter comprising:

a memory for storing a plurality of neighboring inverse-log values and a plurality of delta values, the memory providing as output a neighboring inverse-log value and a delta value which correspond to a first bit slice of the input signal;

a multiplier for multiplying a second bit slice of the input signal by the delta value to produce a correction factor representing a first term divided by an interval value; and

an adder for summing the correction factor and the neighboring inverse-log value to produce the inverse-log signal.

22. The inverse-logarithm converter of claim 21, wherein the pluralities of neighboring inverse-log values and delta values are pre-computed for a plurality of base point values within a pre-selected domain of input signals.

23. The inverse-logarithm converter of claim 22, wherein ones of the neighboring log values and delta values corresponding to a same base point are located at a common address in the memory.

24. A computing device, which comprises:

a processing unit for executing a computer operation which utilizes a inverse-log signal;

a computer memory for storing a computer program which includes the computer operation;

a bus for connecting the processing unit and the computer memory; and

a inverse-logarithm converter which receives a digital input signal and includes;

a memory for storing a plurality of neighboring inverse-log values and a plurality of delta values, the memory providing as output a neighboring inverse-log value and a delta value which correspond to a first bit slice of the digital input signal;

a multiplier for multiplying a second bit slice of the digital input signal by the delta value to produce a correction factor representing a first term divided by an interval value; and

an adder for summing the correction factor and the neighboring inverse-log value to produce the inverse-log signal.

25. The computing device of claim 24, wherein the pluralities of neighboring inverse-log values and delta values are pre-computed for a plurality of base point values within a pre-selected domain of input signals.

26. The computing device of claim 25, wherein ones of the neighboring log values and delta values corresponding to a same base point are located at a common address in the memory.