Register protection structure for FPGA

• US 5,600,597 A
• Filed: 06/06/1995
• Issued: 02/04/1997
• Est. Priority Date: 05/02/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kean, Thomas A., Wilkie, William A.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/486,176
• Time in Patent Office: 609 Days
• Field of Search: 365/189.08, 326/38, 326/39, 377/28
• US Class Current: 365/189.08
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/17768 for security

Abstract

In an FPGA having registers which are part of a user'"'"'s logic functions and a configuration memory which is read and written through an addressing structure, a register protect circuit controllably protects the contects of these user logic registers from being modified by signals from the user'"'"'s logic, allows these registers to be written by a microprocessor through the configuration memory addressing structure, and allows both the user'"'"'s registers and lines which provide combinational signals to be read by a microprocessor through the configuration memory addressing structure.

Claims

1. A register protect structure comprising:

a register having a data input terminal for receiving an input signal D, a register output terminal for providing a register output signal Q, and a clock input terminal;

means for generating a user logic signal;

means for accessing said register input terminal and register output terminal through configuration memory accessing lines;

means for selecting said input signal D from any one of said user logic signal, said configuration memory accessing lines, and said register output signal Q; and

register protect means for preventing said user logic signal from being selected by said means for selecting.

2. A register protect structure as in claim 1 in which said register further has a clear input terminal for clearing said output signal Q in response to a clear signal.

3. A register protect structure as in claim 2 further comprising:

means for preventing said clear signal from being passed to said clear input terminal.

4. A register protect structure comprising:

a register having a data input terminal for receiving an input signal D, a register output terminal for providing a register output signal O, a clock input terminal, and a clear input terminal for clearing said output signal O in response to a clear signal;

means for generating a user logic signal;

means for accessing said register input terminal and register output terminal through configuration memory accessing lines;

means for selecting said input signal D from any of said user logic signal, said configuration memory access lines, and said register output signal O; and

register protect means for preventing said user logic signal from being selected by said means for selecting;

means for preventing said clear signal from being massed to said clear in terminal, said means for preventing said clear signal from being passed to said clear input terminal comprising a logic gate which receives both said clear signal and a signal from said register protect means and passes said clear signal to said clear input terminal only when said signal from said register protect means is not asserted.