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Memory cell and wordline driver for embedded DRAM in ASIC process

  • US 5,600,598 A
  • Filed: 12/14/1994
  • Issued: 02/04/1997
  • Est. Priority Date: 12/14/1994
  • Status: Expired due to Term
First Claim
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1. A DRAM charge storage structure comprising a p-channel access FET in an n- doped well of a p- doped substrate, a p- channel charge storage capacitor, conductive means connecting a gate of the charge storage capacitor to a drain of the FET, and means for applying a boosted word line voltage to a gate of the FET, the charge capacitor having p+ doped source/drain region diffused into the n- well, means for connecting the p+ doped region to a voltage source Vpp which is high enough to maintain the channel of the charge storage capacitor upon the capacitor receiving charge defining any of 0 or 1 logic levels, an n doped region diffused into the n- well, and means for connecting the n doped region to a voltage source which is sufficiently high so as to reduce sub-threshold leakage through the p-channel access FET.

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