Memory cell and wordline driver for embedded DRAM in ASIC process
First Claim
1. A DRAM charge storage structure comprising a p-channel access FET in an n- doped well of a p- doped substrate, a p- channel charge storage capacitor, conductive means connecting a gate of the charge storage capacitor to a drain of the FET, and means for applying a boosted word line voltage to a gate of the FET, the charge capacitor having p+ doped source/drain region diffused into the n- well, means for connecting the p+ doped region to a voltage source Vpp which is high enough to maintain the channel of the charge storage capacitor upon the capacitor receiving charge defining any of 0 or 1 logic levels, an n doped region diffused into the n- well, and means for connecting the n doped region to a voltage source which is sufficiently high so as to reduce sub-threshold leakage through the p-channel access FET.
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Abstract
A DRAM charge storage structure including a p-channel access FET in an n- doped well of a p- doped substrate, a p- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.
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Citations
5 Claims
- 1. A DRAM charge storage structure comprising a p-channel access FET in an n- doped well of a p- doped substrate, a p- channel charge storage capacitor, conductive means connecting a gate of the charge storage capacitor to a drain of the FET, and means for applying a boosted word line voltage to a gate of the FET, the charge capacitor having p+ doped source/drain region diffused into the n- well, means for connecting the p+ doped region to a voltage source Vpp which is high enough to maintain the channel of the charge storage capacitor upon the capacitor receiving charge defining any of 0 or 1 logic levels, an n doped region diffused into the n- well, and means for connecting the n doped region to a voltage source which is sufficiently high so as to reduce sub-threshold leakage through the p-channel access FET.
- 2. A DRAM charge storage structure comprising a charge storage capacitor means connected between a high voltage source Vpp and a source-drain circuit of a storage cell access FET, the source-drain circuit being connected to a wordline, the cell access FET being comprised of first and second p doped regions separated by a channel and contained in an n- doped region of a p- doped substrate, the capacitor being comprised of an FET having a conductive gate region insulated from and disposed above the channel and a third p-doped region adjacent to the channel, means for connecting the conductive gate region of the capacitor to the second p doped region of the FET spaced from the conductive region, an n doped region contained in the n- doped region spaced from the third p doped region, means for applying the high voltage Vpp to the n doped region and the third p doped region, means for connecting the bit line to the first p doped region, and means for applying a voltage from the wordline to a gate of the storage cell access FET which is boosted from the wordline voltage Vdd.
Specification