Memory cell and wordline driver for embedded DRAM in ASIC process

• US 5,600,598 A
• Filed: 12/14/1994
• Issued: 02/04/1997
• Est. Priority Date: 12/14/1994
• Status: Expired due to Term

• Current Assignee: Trace Step Holdings LLC (Intellectual Ventures LLC)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Skjaveland, Karl, Gillingham, Peter B.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/355,956
• Time in Patent Office: 783 Days
• Field of Search: 365/189.11, 365/189.09, 365/230.06, 365/149, 257/296, 257/313, 257/306
• US Class Current: 365/189.11
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A DRAM charge storage structure including a p-channel access FET in an n^- doped well of a p^- doped substrate, a p^- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.

Claims

1. A DRAM charge storage structure comprising a p-channel access FET in an n^- doped well of a p^- doped substrate, a p^- channel charge storage capacitor, conductive means connecting a gate of the charge storage capacitor to a drain of the FET, and means for applying a boosted word line voltage to a gate of the FET, the charge capacitor having p⁺ doped source/drain region diffused into the n^- well, means for connecting the p⁺ doped region to a voltage source V_pp which is high enough to maintain the channel of the charge storage capacitor upon the capacitor receiving charge defining any of 0 or 1 logic levels, an n doped region diffused into the n^- well, and means for connecting the n doped region to a voltage source which is sufficiently high so as to reduce sub-threshold leakage through the p-channel access FET.

4. A structure as defined in claim 1 in which the FET and the means for applying the boosted wordline voltage are all formed of only p channel type FETs.

5. A structure as defined in claim 1 in which the means for applying the boosted wordline voltage is formed of only p channel type FETs.

2. A DRAM charge storage structure comprising a charge storage capacitor means connected between a high voltage source V_pp and a source-drain circuit of a storage cell access FET, the source-drain circuit being connected to a wordline, the cell access FET being comprised of first and second p doped regions separated by a channel and contained in an n^- doped region of a p^- doped substrate, the capacitor being comprised of an FET having a conductive gate region insulated from and disposed above the channel and a third p-doped region adjacent to the channel, means for connecting the conductive gate region of the capacitor to the second p doped region of the FET spaced from the conductive region, an n doped region contained in the n^- doped region spaced from the third p doped region, means for applying the high voltage V_pp to the n doped region and the third p doped region, means for connecting the bit line to the first p doped region, and means for applying a voltage from the wordline to a gate of the storage cell access FET which is boosted from the wordline voltage V_dd.

3. A structure as defined in claim 2 in which the FETs and the means for applying the boosted wordline voltage are all formed of only p channel type FETs.