Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same
DCFirst Claim
1. A method of operating a memory device including a plurality of multiplexed data/address input/output terminals, an array of memory cells, and circuitry for accessing selected ones of the memory cells in response to received row and column address bits, the method comprising the steps of:
- substantially simultaneously inputting said row address bit and column address bit during an address cycle, at least one of said row and column address bits input through a selected one of the multiplexed terminals; and
accessing ones of the memory cells addressed by the row and column bits through selected ones of the multiplexed terminals during a data access cycle.
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Abstract
A method of operating a memory device including a plurality of data/address input/output terminals, an array of memory cells and circuitry for accessing selected ones of the memory cells in response to received address bits. At least one row address bit and at least one column address bit are substantially simultaneously input during an address cycle, at least one of the address bits being input through a selected one of the multiplexed terminals. The memory cells addressed by the row and column bits are then accessed through selected ones of the multiplexed terminals during a data access cycle.
66 Citations
23 Claims
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1. A method of operating a memory device including a plurality of multiplexed data/address input/output terminals, an array of memory cells, and circuitry for accessing selected ones of the memory cells in response to received row and column address bits, the method comprising the steps of:
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substantially simultaneously inputting said row address bit and column address bit during an address cycle, at least one of said row and column address bits input through a selected one of the multiplexed terminals; and accessing ones of the memory cells addressed by the row and column bits through selected ones of the multiplexed terminals during a data access cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating a random access memory comprising the steps of:
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during a precharge period, substantially simultaneously inputting row and column address bits, at least some of said row and column address bits input through a plurality of multiplexed data/address input/output terminals; and during an active period,performing a random access to memory cells addressed by the input row and column address bits through the multiplexed terminals. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A random access memory comprising:
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a plurality of terminals for receiving substantially simultaneously row and column address bits during an address cycle, at least some of said plurality of terminals comprising multiplexed terminals for exchanging data during a data access cycle; an array of rows and columns of memory cells; and addressing circuitry for accessing locations within said array in response to received row and column address bits. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A memory system comprising:
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a non-multiplexed address bus; a data bus; and a random access memory comprising; a plurality of terminals for receiving substantially simultaneously row and column address bits presented on said non-multiplexed address bus during an address cycle, at least some of said plurality of terminals comprising multiplexed terminals for exchanging data with said data bus during a data access cycle; an array of rows and columns of memory cells; and addressing circuitry for accessing locations within said array during said data access cycle in response to received row and column address bits. - View Dependent Claims (22, 23)
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Specification