Trellis coded modulation system for digital television signal

• US 5,600,677 A
• Filed: 01/16/1996
• Issued: 02/04/1997
• Est. Priority Date: 07/08/1994
• Status: Expired due to Term

• Current Assignee: Zenith Electronics Corporation (LG Corporation)
• Original Assignee: Zenith Electronics Corporation (LG Corporation)
• Inventors: Citta, Richard W., Willming, David A.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/586,441
• Time in Patent Office: 385 Days
• Field of Search: 375/296, 375/298, 375/308, 375/295, 375/285, 375/264, 375/263, 375/262, 375/265, 375/290, 348/470, 348/608, 348/607, 332/103
• US Class Current: 375/296
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 27/3416 in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence

Abstract

A trellis coded modulation system comprises a first coder for convolutionally coding a first input data bit X₁ for deriving first and second output bits Z₀ and Z₁. A second coder precodes a second input data bit X₂ for deriving an output bit Z₂. The output bits Z₀, Z₁ and Z₂ are mapped into corresponding one-dimensional multi-value symbols, wherein the output bits Z₀, Z₁ identify respective subsets of the symbols, each of the subsets comprising two equally spaced symbol values, and the output bits Z₁, Z₂ identify respective pairs of the symbols, each of the pairs comprising two adjacent symbol values.

Claims

1. A trellis coded modulator comprising:

means for convolutionally coding a first input data bit X₁, for deriving first and second output bits Z₀ and Z₁ ;

means for precoding one or more second input data bits X₂ -X_N for deriving respective output bits Z₂ -Z_N ; and

means for mapping the output bits Z₀, Z₁, Z₂ -Z_N into corresponding one-dimensional multi-value symbols, wherein said symbols form a phase variant symbol constellation and wherein the output bits Z₀, Z₁ identify respective subsets of said symbols, each of said subsets comprising two or more equally spaced symbol values, and the output bits Z₁, Z₂ -Z_N identify respective pairs of said symbols, each of said pairs comprising two adjacent symbol values.

2. The trellis coded modulator of claim 1 wherein said means for precoding comprises means for precoding one second input data bit X₂ for deriving an output bit Z₂ and wherein said means for mapping comprises means for mapping output bits Z₀, Z₁, Z₂ into corresponding eight-value symbols, each of said subsets comprising two equally spaced symbol values and the output bits Z₁, Z₂ identifying said respective pairs of said symbols.

3. The trellis coded modulator of claim 1 wherein said multi-value symbols comprise symbols having a plurality of distinct amplitude levels.

4. The trellis coded modulator of claim 3 wherein said amplitude levels are symmetrical about a zero level and including means for offsetting the amplitude of each of said symbols by a predetermined amount for providing a pilot component.

5. The trellis coded modulator of claim 2 wherein said eight-value symbols comprise symbols having eight distinct amplitude levels.

6. The trellis coded modulator of claim 1 including means for supplying said input data bits X₁, X₂ -X_N at a predetermined symbol rate and wherein said precoder and convolution coder each include one or more M symbol interval delay elements, whereby said output bits Z₀, Z₁, Z₂ -Z_N are provided in the form of M interleaved groups of separately coded bits.

7. The trellis coded modulator of claim 6 wherein M is equal to 12.

8. The trellis coded modulator of claim 1 wherein the convolution coder comprises a 4-state, rate 1/2, feedback, systematic convolution coder.

9. The trellis coded modulator of claim 2 wherein said precoder comprises means for modulo-2 adding a current input data bit X₂ with the input data bit X₂ occurring M input data bit intervals prior thereto.

10. The trellis coded modulator of claim 9 wherein M is equal to 12.

11. A trellis coded modulator comprising:

means for supplying two or more input data bits X₁, X₂ -X_N at a predetermined symbol rate;

a first coder including at least one delay element M symbol intervals in length for convolutionally coding input bit X₁ for deriving first and second output bits Z₀ and Z₁ ;

a second coder including a delay element M symbol intervals in length for precoding input bits X₂ -X_N for deriving respective output bits Z₂ -Z_N, the output bits Z₀, Z₁, Z₂ -Z_N thereby being provided in the form of M interleaved groups of separately coded bits; and

means for mapping the output bits Z₀, Z₁, Z₂ -Z_N into corresponding one-dimensional multi-value symbols each having a different amplitude level, wherein said symbols form a phase variant symbol constellation, the output bits Z₀, Z₁ identifying respective subsets of said symbols, wherein the difference between the amplitude levels of the symbols of each of said subsets are equal, and the output bits Z₁, Z₂ -Z_N identifying respective pairs of said symbols each comprising two adjacent amplitude levels.

12. The trellis coded modulator of claim 11 wherein M is equal to 12.

13. The trellis coded modulator of claim 11 wherein said means for supplying comprises means for supplying two input data bits X₁, X₂, said second coder precoding input bit X₂ for deriving an output bit Z₂ and said means for mapping comprising means for mapping output bits Z₀, Z₁, Z₂ into corresponding 8-level symbols, the output bits Z₁, Z₂ identifying respective pairs of said symbols each comprising two adjacent amplitude levels.

14. A trellis coded modulator comprising:

means for convolutionally coding a first input data bit X₁, for deriving first and second output bits Z₀ and Z₁ ;

means for precoding one or more second input data bits X₂ -X_N for deriving respective output bits Z₂ -Z_N ;

means for developing an output signal by mapping the output bits Z₀, Z₁, Z₂ -Z_N into corresponding one-dimensional multi-value symbols, wherein said symbols form a phase variant symbol constellation and wherein the output bits Z₀, Z₁ identify respective subsets of said symbols, each of said subsets comprising two or more equally spaced symbol values, and the output bits Z₁, Z₂ -Z_N identify respective pairs of said symbols, each of said pairs comprising two adjacent symbol values;

means for inserting a synchronization signal in said output signal at selected time intervals; and

means for preventing said means for precoding and said means for convolutionally coding from changing state during said selected time intervals.

15. The trellis coded modulator of claim 14 wherein said means for precoding comprises means for precoding one second input data bit X₂ for deriving an output bit Z₂ and wherein said means for mapping comprises means for mapping output bits Z₀, Z₁, Z₂ into corresponding eight-value symbols, each of said subsets comprising two equally spaced symbol values and the output bits Z₁, Z₂ identifying said respective pairs of said symbols.

16. The trellis coded modulator of claim 14 wherein said multi-value symbols comprise symbols having a plurality of distinct amplitude levels.

17. The trellis coded modulator of claim 16 wherein said amplitude levels are symmetrical about a zero level and including means for offsetting the amplitude of each of said symbols by a predetermined amount for providing a pilot component.

18. The trellis coded modulator of claim 15 wherein said eight-value symbols comprise symbols having eight distinct amplitude levels.

19. The trellis coded modulator of claim 14 including means for supplying said input data bits X₁, X₂ -X_N at a predetermined symbol rate and wherein said precoder and convolution coder each include one or more M symbol interval delay elements, whereby said output bits Z₀, Z₁, Z₂ -Z_N are provided in the form of M interleaved groups of separately coded bits.

20. The trellis coded modulator of claim 19 wherein M is equal to 12.

21. The trellis coded modulator of claim 14 wherein the convolution coder comprises a 4-state, rate 1/2, feedback, systematic convolution coder.

22. The trellis coded modulator of claim 15 wherein said precoder comprises means for modulo-2 adding a current input data bit X₂ with the input data bit X₂ occurring M input data bit intervals prior thereto.

23. The trellis coded modulator of claim 22 wherein M is equal to 12.

24. A trellis coded modulator comprising:

means for supplying two or more input data bits X₁, X₂ 14 X_N at a predetermined symbol rate;

a first coder including at least one delay element M symbol intervals in length for convolutionally coding input bit X₁ for deriving first and second output bits Z₀ and Z₁ ;

a second coder including a delay element M symbol intervals in length for precoding input bits X₂ -X_N for deriving respective output bits Z₂ -Z_N, the output bits Z₀, Z₁, Z₂ -Z_N thereby being provided in the form of M interleaved groups of separately coded bits; and

means for developing an output signal by mapping the output bits Z₀, Z₁, Z₂ -Z_N into corresponding one-dimensional multi-value symbols each having a different amplitude level, wherein said symbols form a phase variant symbol constellation, the output bits Z₀, Z₁ identifying respective subsets of said symbols, wherein the difference between the amplitude levels of the symbols of each of said subsets are equal, and the output bits Z₁, Z₂ -Z_N identifying respective pairs of said symbols each comprising two adjacent amplitude levels;

means for inserting a synchronization signal in said output signal at selected time intervals; and

means for preventing said means for precoding and said means for convolutionally coding from changing state during said selected time intervals.

25. The trellis coded modulator of claim 24 wherein M is equal to 12.

26. The trellis coded modulator of claim 24 wherein said means for supplying comprises means for supplying two input data bits X₁, X₂, said second coder precoding input bit X₂ for deriving an output bit Z₂ and said means for mapping comprising means for mapping output bits Z₀, Z₁, Z₂ into corresponding 8-level symbols, the output bits Z₁, Z₂ identifying respective pairs of said symbols each comprising two adjacent amplitude levels.