Communication data format

• US 5,600,683 A
• Filed: 05/01/1995
• Issued: 02/04/1997
• Est. Priority Date: 05/01/1995
• Status: Expired due to Term

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bierach, Kirk B., Shi, Ximing
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US08/432,257
• Time in Patent Office: 645 Days
• Field of Search: 375/284, 375/285, 375/363, 375/364, 375/366, 375/368, 370/105.1, 370/105.4, 370/106
• US Class Current: 375/363
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Abstract

A new data format used in a communication system employing binary phase shift keying modulation and demodulation is described. The data format provides for a frame comprising a plurality of variable data bits and synchronization bits. The number of variable data bits in the data format of the present invention is more than the number of synchronization bits. The data format preferably includes a CRC field for error detection. In order to uniquely decode the information contained in the frame, the inverse of frame should not be a valid frame. A method for detecting invalid frames is also disclosed.

Claims

1. A system comprising:

a device containing digital data arranged to include a plurality of variable data bits and synchronization bits, the number of said variable data bits being more than the number of said synchronization bits; and

a modulation circuit coupled to said device for generating modulated signals by modulating said digital data in accordance with a binary phase shift keying technique;

a demodulation circuit for generating demodulated signals from said modulated signals;

a decoder for correctly recovering said variable data bits from said demodulated signals, said decoder includes;

means for verifying that said demodulated signals contain said synchronization bits;

means for forming a complement of said demodulated signals; and

means for extracting said variable data bits.

2. The digital data of claim 1 further including a CRC field.

3. The digital data of claim 1 wherein said synchronization bits include a plurality of distributed synchronization bits and a fixed synchronization field having a plurality of contiguous synchronization bits.

4. The system of claim 1 wherein said variable data bits are arranged into a plurality of fields.

5. A method for determining whether a data frame is a valid frame, said valid frame having synchronization bits at a first set of predetermined positions and variable data bits at a second set of predetermined positions, comprising the steps of:

scanning said first set of predetermined positions of said data frame;

if said first set of predetermined positions contains said synchronization bits, extracting said variable data bits located at said second set of predetermined positions;

if said first set of predetermined positions does not contain said synchronization bits;

forming a complementary frame by inverting all bits in said data frame;

scanning said first set of predetermined positions of said complementary frame;

if said first set of predetermined positions of said complementary frame contains said synchronization bits, extracting said variable data bits located at said second set of predetermined positions of said complementary frame; and

if said first set of predetermined positions of said complementary frame does not contain said synchronization bits, discarding said data frame.

6. The method of claim 5 wherein said valid frame further includes a third set of predetermined positions for storing a CRC value, said method further comprising:

computing a first CRC value for said variable data bits at said data frame; and

extracting said variable data bits located at said second set of predetermined positions of said data frame if said first CRC value is equal to said CRC value at said third set of predetermined positions.

7. The method of claim 6 further comprising the steps of:

computing a second CRC value for bits in said complementary frame located in said second set of predetermined positions; and

discarding said data frame if said second CRC value is different from a CRC value designated by said third set of predetermined positions of said complementary frame.

8. The method of claim 5 further comprises:

assembling a plurality of data frames;

comparing bits in corresponding positions in said plurality of data frames; and

discarding said plurality of data frames if said comparing step indicates that one or more corresponding bits in said plurality of data frames are not the same.

9. The method of claim 5 wherein said variable data bits are divided into a plurality of fields.

10. A method for generating a valid frame having synchronization bits at a first set of predetermined positions and variable data bits at a second set of predetermined positions, comprising the steps of:

assembling a test frame by placing synchronization bits at said first set of predetermined positions and variable data bits at said second set of predetermined positions;

forming a complementary frame by inverting bits in said test frame; and

discarding said test frame if the bits in said first set of predetermined positions of said complementary frame are the same as said synchronization bits.

11. The method of claim 10 further comprising the steps of

rotating said test frame one bit at a time;

and

at each rotation, performing the following steps;

forming a complementary rotated frame by inverting bits in said rotated frame; and

discarding said test frame if the bits in said first set of predetermined positions of said complementary rotated frame are the same as said synchronization bits.

12. The method of claim 10 wherein said variable data bits are arranged into a plurality of fields.