Digital test and maintenance architecture

• US 5,600,788 A
• Filed: 01/19/1994
• Issued: 02/04/1997
• Est. Priority Date: 01/19/1994
• Status: Expired due to Term

• Current Assignee: Kiribati Wireless Ventures LLC (Intellectual Ventures LLC)
• Original Assignee: Martin Marietta Corporation
• Inventors: Thorne, James A., Lofgren, John D.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elmore, Stephen C.
• Application Number:
  US08/182,835
• Time in Patent Office: 1,112 Days
• Field of Search: 371/16.1, 395/575, 364/579, 364/580, 364/267.4
• US Class Current: 714/31
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A testing device has an architecture including a board test interface for coupling to test points on a circuit board; a programmable processor, coupled to the board test interface, for controlling a test of the circuit board via the board test interface; and a first communications interface, coupled to the programmable processor, for coupling to a like first communications interface located on another testing device. The programmable processor uses the first communications interface for communicating test commands and test results with the other testing device, so that a complete test of a system can be produced. The testing device may further include a control port, coupled to the programmable processor, for communicating system test commands between a host processor and the programmable processor. In response to a first system test command received from the host processor via the control port, the programmable processor may use the first communications interface to send a second test command to another testing device. Also, a number of identical testing devices, each located on a corresponding one of a number of circuit boards in a system, may use the first communications interface to transmit test results to one of the testing devices, designated as a master coordinating device. The master coordinating device then forwards all of the test results to a host processor for analysis. The entire testing device may be fabricated as a single integrated circuit, in order to provide great testability without occupying a great deal of circuit board space.

Claims

1. A testing device comprising:

board test interface means for coupling to test points on a circuit board;

programmable processing means, coupled to the board test interface means, for controlling a test of the circuit board via the board test interface means;

first communications interface means, coupled to the programmable processing means, for multi-master coupling to a like first communications interface means located on another testing device,

wherein the programmable processing means uses the first communications interface means for communicating test commands and test results with said another testing device, and

wherein the testing device is fabricated as an integrated circuit.

2. The testing device of claim 1, further comprising a control port, coupled to the programmable processing means, for communicating test commands between a host processor and the programmable processing means.

3. The testing device of claim 2, wherein the programmable processing means receives a first system test command from the control port, and in response thereto, uses the first communications interface means to send a second test command to said another testing device.

4. The testing device of claim 2, wherein the programmable processing means receives from the first communications interface means test results produced by said another testing device, and in response thereto uses the control port to forward the test results to the host processor.

5. The testing device of claim 2, further comprising dual port memory means including a first memory port and a second memory port, the first memory port being coupled to the control port, and the second memory port being coupled to the first communications interface means.

6. The testing device of claim 5, further comprising a direct memory access controller, controlled by the programmable processing means and coupled to the dual port memory means and to the first communications interface means for facilitating a data transfer therebetween.

7. The testing device of claim 1, further comprising second communications interface means, coupled to the programmable processing means, for coupling to a like second communications interface means located on another testing device,

wherein the programmable processing means uses the second communications interface means for communicating test commands and test results with said another testing device.

8. The testing device of claim 7, further comprising:

clock input means for receiving an externally generated clock signal;

synchronizing means, coupled to said clock input means, to said first communications interface means and to said second communications interface means, for controlling generation of signals appearing on said first communications interface means and on said second communications interface means;

clock redistribution means, coupled to said clock input means, for redistributing said received externally generated clock signal to said another testing device;

reset input means for receiving an externally generated reset signal; and

reset redistribution means, coupled to said reset input means, for redistributing said received clock signal to said another testing device.

9. The testing device of claim 1, wherein:

the board test interface means is an IEEE standard 1149.1 controller; and

the first communications interface means operates in accordance with ANSI/IEEE standard 802.4.

10. The testing device of claim 1, wherein:

the board test interface means is an IEEE standard 1149.1 controller; and

the first communications interface means operates in accordance with a synchronous data link control protocol.

11. The testing device of claim 7, wherein:

the board test interface means is an IEEE standard 1149.1 controller;

the first communications interface means operates in accordance with ANSI/IEEE standard 802.4; and

the second communications interface means is an IEEE standard 1149.5 interface.

12. The testing device of claim 7, wherein:

the board test interface means is an IEEE standard 1149.1 controller;

the first communications interface means operates in accordance with a synchronous data link control protocol; and

the second communications interface means is an IEEE standard 1149.5 interface.

13. A testing system, comprising:

first and second testing devices, each comprising;

board test interface means for coupling to test points on a circuit board;

programmable processing means, coupled to the board test interface means, for controlling a test of the circuit board via the board test interface means; and

first communications interface means, coupled to the programmable processing means, for multi-master coupling to a like first communications interface means located on another testing device,

wherein the programmable processing means uses the first communications interface means for communicating test commands and test results with said another testing device, and

wherein the first communications interface means of the first testing device is coupled to the first communications interface means of the second testing device;

wherein the first testing device is fabricated as a first integrated circuit, and the second testing device is fabricated as a second integrated circuit.

14. The testing system of claim 13, wherein each of said first and second testing devices further comprises a control port, coupled to the programmable processing means, for communicating system test commands between a host processor and the programmable processing means.

15. The testing system of claim 14, wherein the programmable processing means of the first testing device receives a first system test command from the control port, and in response thereto, uses the first communications interface means to send a second test command to the second testing device.

16. The testing system of claim 14, wherein the programmable processing means of the first testing device receives from the first communications interface means test results produced by the second testing device, and in response thereto uses the control port to forward the test results to the host processor.

17. The testing system of claim 14, wherein each of the first and second testing devices further comprises dual port memory means including a first memory port and a second memory port, the first memory port being coupled to the control port, and the second memory port being coupled to the first communications interface means.

18. The testing system of claim 17, wherein each of the first and second testing devices further comprises a direct memory access controller, controlled by the programmable processing means and coupled to the dual port memory means and to the first communications interface means for facilitating a data transfer therebetween.

19. The testing system of claim 17, wherein the first testing device is connected to a first circuit board, and wherein the second testing device is connected to a second circuit board.

20. The testing system of claim 19, wherein the first and second circuit boards are connected to a common backplane.

21. The testing system of claim 19, wherein the first circuit board is connected to a first backplane, and wherein the second circuit board is connected to a second backplane.

22. The testing system of claim 13,

wherein each of the first and second testing devices further comprises second communications interface means, coupled to the programmable processing means, for coupling to a like second communications interface means located on another testing device,

wherein the programmable processing means uses the second communications interface means for communicating test commands and test results with said another testing device, and

wherein the second communications interface means of the first testing device is coupled to the second communications interface means of the second testing device.

23. The testing system of claim 22, wherein:

the board test interface means is an IEEE standard 1149.1 controller;

the first communications interface means operates in accordance with ANSI/IEEE standard 802.4; and

the second communications interface means is an IEEE standard 1149.5 interface.

24. The testing system of claim 22, wherein:

the board test interface means is an IEEE standard 1149.1 controller;

the first communications interface means operates in accordance with a synchronous data link control protocol; and

the second communications interface means is an IEEE standard 1149.5 interface.

25. The testing system of claim 13, wherein:

the board test interface means is an IEEE standard 1149.1 controller; and

the first communications interface means operates in accordance with ANSI/IEEE standard 802.4.

26. The testing system of claim 13, wherein:

the board test interface means is an IEEE standard 1149.1 controller; and

the first communications interface means operates in accordance with a synchronous data link control protocol.