Methods and apparatus for translating incompatible bus transactions

• US 5,600,802 A
• Filed: 03/14/1994
• Issued: 02/04/1997
• Est. Priority Date: 03/14/1994
• Status: Expired due to Term

• Current Assignee: Apple Computer Incorporated (Apple Inc.)
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Yazdy, Farid A., Dhuey, Michael J.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/212,457
• Time in Patent Office: 1,058 Days
• Field of Search: 395/325, 395/500, 395/375, 395/282, 371/22.3, 361/683
• US Class Current: 710/301
• CPC Class Codes: G06F 13/4063 Device-to-bus coupling

Abstract

Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

Claims

1. A method of operating a computer system having a first processor and a processor direct bus whereby said first processor is replaced with a second processor, comprising the steps of:

coupling said second processor to said processor direct bus;

resetting said first processor;

generating, and applying via said processor direct bus to said first processor, a shutdown signal sequence to shut down said first processor and meanwhile asserting a reset signal to keep said first processor in a reset state;

de-asserting said reset signal; and

granting control of said computer system to said second processor;

wherein the step of generating comprises applying the shutdown signal sequence to a JTAG test port of the first processor.

2. A plug-in card, having a first processor, for operating a computer system, having a second processor and a processor direct bus, comprising:

means for coupling said first processor to said processor direct bus;

means for resetting said second processor;

means for generating, and means for applying said processor direct bus to said second processor, a shutdown sequence to shut down said second processor and meanwhile having means for asserting a reset signal to keep said second processor in a reset state;

means for de-asserting said reset signal; and

means for granting control of said computer system to said first processor;

wherein the means for generating comprises means for applying the shutdown signal sequence to a JTAG test port of the second processor.