Scaleable very long instruction word processor with parallelism matching

• US 5,600,810 A
• Filed: 12/09/1994
• Issued: 02/04/1997
• Est. Priority Date: 12/09/1994
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Electric Research Laboratories, Inc. (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Electric Information Technology Center America, Inc. (Mitsubishi Electric Corporation)
• Inventors: Ohkami, Takahide
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/352,927
• Time in Patent Office: 788 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/375, 395/700, 395/800
• US Class Current: 712/226
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A system is provided to increase the efficiency of a VLIW, Very Long Insttion Word, processor which matches its level of parallelism, LOP, to the LOP of the executable code before executing the code'"'"'s fixed-length VLIW instructions, so that object-level code compatibility is kept for different processor implementations of the same VLIW architecture required for different applications. Matching is accomplished either by reducing the LOP of the processor via inactivating the processor'"'"'s functional units, or by effectively reducing the LOP of the executable code via the processor executing the sequential portions of each VLIW instruction in the code, with the length of the portions equal to or less than the number of operations that the processor can handle as a VLIW instruction.

Claims

1. Apparatus for increasing the efficiency of a VLIW processor having functional units for the parallel processing of VLIW instructions embedded in compiled executable code, comprising:

means for establishing the level of parallelism of said processor;

means for establishing the level of parallelism of said executable code;

means when the level of parallelism of said processor exceeds that of said executable code for inactivating that number of said functional units which brings the level of parallelism of said processor to match that of said executable code; and

,

means when the level of parallelism of said processor is less than that of said executable code for sequentially reading out portions of said executable code processable by the existing functional units of said processor whereby the level of parallelism of said processor and said executable code are matched.

2. The Apparatus of claim 1 wherein said executable code has fixed length instructions.

3. The Apparatus of claim 2 wherein the level of parallelism is equal to the number of operations that are mutually independent such that said operations can be performed in parallel.

4. The Apparatus of claim 3 wherein said instructions have N operation fields capable of taking any unit instruction and corresponding to N-long instructions, with each of said operation fields specifying one unit instruction, said processor executing in parallel N operations specified by N unit instructions in an N-long instruction, whereby there is no restriction on allocating any instruction to a field for achieving parallel processing.

5. The Apparatus of claim 4 wherein the level of parallelism is equal to N.

6. The Apparatus of claim 5 wherein said executable code has equal portions of executable code plus a remainder portion and wherein said sequential read out means includes means for first reading out all equal portions followed by read out of said remainder portion.

7. The Apparatus of claim 6 wherein the level of parallelism of said processor and said executable code are chosen as powers of 2.

8. The Apparatus of claim 5 wherein said executable code has a level of parallelism N, and wherein said means for reading out portions of said executable code includes means for executing sequences of N unit instructions.

9. The Apparatus of claim 2 wherein the length of the portions of said executable code read out to said processor are equal or less than the number of operations that said processor can handle as an instruction.

10. Apparatus for increasing the efficiency of a VLIW processor having functional units for the parallel processing of VLIW instructions embedded in compiled executable code, comprising:

means for establishing the level of parallelism of said processor;

means for establishing the level of parallelism of said executable code; and

,

means when the level of parallelism of said processor exceeds that of said executable code for inactivating that number of said functional units which brings the level of parallelism of said processor to match that of said executable code.

11. Apparatus for increasing the efficiency of a VLIW processor having functional units for the parallel processing of VLIW instructions embedded in compiled executable code, comprising:

means for establishing the level of parallelism of said processor;

means for establishing the level of parallelism of said executable code; and

,

means when the level of parallelism of said processor is less than that of said executable code for sequentially reading out portions of said executable code processable by the existing functional units of said processor whereby the level of parallelism of said processor and said executable code are matched.