Vector move instruction in a vector data processing system and method therefor

• US 5,600,811 A
• Filed: 08/03/1995
• Issued: 02/04/1997
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Spielman, Jason, Huang, Yee-Wei, Gallup, deceased, Michael G., Seaton, Robert W. Jr., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/510,895
• Time in Patent Office: 551 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/203
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A "vnmvh" instruction reduces a substantial number of instructions and the temporary use of a register in a software code which executes nested conditional constructs in a vector data processor (10). When the vnmvh instruction is executed, all processing elements in the vector data processor participate in the function regardless of a setting of a status bit (Vt bit) (FIG. 6). During execution of the vnmvh instruction, the least significant bits of vector register specified in an operand are negated and moved into a plurality of history bits (Vh bits) (FIG. 6). The functionality provided by execution of vnmvh instruction allows a user to execute a nested conditional construct efficiently and effectively.

Claims

1. A method for executing an instruction in a data processor, comprising the steps of:

storing a first vector value in a vector register;

storing a digital data value in a processing element;

storing an enable value in a first storage circuit, the enable value corresponding to the processing element, the enable value selectively enabling the processing element to participate in execution of the instruction;

storing a history value in a second storage circuit, the history value corresponding to the processing element, the history value being used to selectively modify the enable value;

receiving the instruction at an input means;

decoding the first instruction to provide a first plurality of control values using an instruction decode means, the instruction decode means being coupled to the input means for receiving the instruction;

negating at least one of a plurality of bits of the first vector value stored in the vector register to provide a negated vector value in response to a first portion of the plurality of control values; and

storing a preselected one of a plurality of bits of the negated vector value in the second storage circuit as the history value in response to a second portion of the plurality of control values.

2. The method of claim 1 wherein the processing element executes the instruction when the enable value is set and when the enable value is negated.

3. The method of claim 1 wherein the modification circuit complements the enable value when the history value is in a first logic state and the modification circuit negates the enable value when the history value is in a second logic state.

4. The method of claim 1 wherein the instruction has a mnemonic form of "vnmvh."

5. The method of claim 1 further comprising the step of:

enabling the processing element to execute a subsequent instruction when the history value is in a first logic state.

6. The method of claim 5 wherein the history value is in the first logic state when the enable value enabled the processing element to participate in execution of the instruction.

7. The method of claim 1 wherein a vector if instruction is executed prior to execution of the instruction, the vector if instruction comparing the digital data value with a comparison value to test a predetermined condition.

8. The method of claim 7 wherein a vector else instruction is executed after execution of the instruction, the vector else instruction executing a preselected operation if the predetermined condition is false.

9. The method of claim 1 further comprising the step of selectively modifying the enable value in response to a logic state of the history value with a modification circuit, the modification circuit being coupled to both the first storage circuit and the second storage circuit.

10. A method for executing an instruction in a data processor, comprising the steps of:

storing a first vector value in a vector register;

storing a plurality of digital data values in a plurality of processing elements, each of the plurality of digital data values corresponding to one of the plurality of processing elements;

storing a plurality of enable values in a first storage circuit, each of the plurality of enable values corresponding to one of the plurality of processing elements and each of the plurality of enable values selectively enables a corresponding one of the plurality of processing elements to participate in execution of the instruction;

storing a plurality of history value in a second storage circuit, each of the plurality of history values corresponding to one of the plurality of processing elements and each of the plurality of history values being used to selectively modify a corresponding one of the plurality of enable values;

receiving the instruction at an input means;

decoding the first instruction to provide a first plurality of control values using an instruction decode means, the instruction decode means being coupled to the input means for receiving the instruction;

negating a portion of a plurality of bits of the first vector value stored in the vector register to provide a negated vector value in response to a first portion of the plurality of control values; and

storing the negated vector value in the second storage circuit as the plurality of history values in response to a second portion of the plurality of control values.

11. The method of claim 10 further comprising the step of:

selectively modifying the enable value in response to a logic state of the history value with a modification circuit, the modification circuit being coupled to both the first storage circuit and the second storage circuit.

12. The method of claim 10 wherein the portion of the plurality of bits of the first vector value is a plurality of low order bits of the first vector value.

13. The method of claim 10 wherein each of the plurality of processing elements executes the instruction when a corresponding one of the plurality of enable values is set and when the corresponding one of the plurality of enable values is negated.

14. The method of claim 10 wherein the modification circuit complements each of the plurality of enable values when the corresponding one of the plurality of history values is in a first logic state and the modification circuit negates each of the plurality of enable values when the corresponding one of the plurality of history values is in a second logic state.

15. The method of claim 10 further comprising the step of:

enabling the plurality of processing elements to execute a subsequent instruction when a corresponding one of the plurality of history values is in a first logic state.

16. The method of claim 15 wherein the corresponding one of the plurality of history values is in the first logic state when a corresponding one of the plurality of enable values enabled a corresponding one of the plurality of processing elements to participate in execution of the instruction.

17. The method of claim 10 wherein a vector if instruction is executed by each of the plurality of processing elements prior to execution of the instruction, the vector if instruction comparing the digital data value stored in each of the plurality of processing elements with a comparison value to test a predetermined condition if a corresponding one of the plurality of enable values is in a first predetermined logic state.

18. The method of claim 17 wherein a vector else instruction is executed by each of the plurality of processing elements after execution of the instruction, the vector else instruction enabling each of the plurality of processing elements to execute a preselected operation if the predetermined condition is false and if a corresponding one of the plurality of history values is in a second predetermined logic state.