Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor

• US 5,600,845 A
• Filed: 07/27/1994
• Issued: 02/04/1997
• Est. Priority Date: 07/27/1994
• Status: Expired due to Fees

• Current Assignee: Seasound LLC
• Original Assignee: Metalithic Systems Incorporated
• Inventors: Gilson, Kent L.
• Primary Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/281,357
• Time in Patent Office: 923 Days
• Field of Search: 395/375, 395/800, 395/775, 326/41
• US Class Current: 712/39
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.

Claims

1. An integrated circuit computing device comprising, in combination:

a dynamically reconfigurable gate array having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and programming means for programming said I/O blocks, said logic blocks, and said routing resources, said programming means defining an appropriate mode of operation for said gate array;

microprocessor means comprising a Reduced Instruction Set Computer (RISC) coupled to an external source and located within said gate array by programming said programming means for processing instructions received from said external source; and

reconfigurable instruction execution means implemented within said gate array by programming said programming means and coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks of said gate array according to said information received.

2. The computing device of claim 1 wherein said I/O blocks comprise input means for providing a plurality of input signals to said logic blocks and said routing resources, and output means for providing a plurality of output signals from said logic blocks and said routing resources to said I/O blocks.

3. The computing device of claim 2 wherein said input means and said output means being implemented within said gate array by programming said programming means.

4. The computing device of claim 1 wherein said programming means comprises Random Access Memory (RAM) and wherein said programming means is programmed by writing data into said RAM.

5. The computing device of claim 4 wherein said RAM for said programming means comprises a shift register and wherein said programming means is programmed by shifting data into said shift register.

6. The computing device of claim 1 wherein said programming means comprises Random Access Memory (RAM) and wherein said programming means is programmed by writing data into said RAM.

7. The computing device of claim 6 wherein said RAM for said programming means comprises a shift register and wherein said programming means is programmed by shifting data into said shift register.

8. An integrated circuit computing device comprising, in combination:

a dynamically configurable gate array having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and Random Access Memory (RAM) programming means for programming said I/O blocks, said logic blocks and said routing resources, said RAM programming means defining an appropriate mode of operation for said gate array;

microprocessor means comprising a Reduced Instruction Set Computer (RISC) coupled to an external source and located within said gate array by programming said RAM programming means for processing instructions received from said external source; and

reconfigurable instruction execution means implemented within said gate array by programming said RAM programming means and coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks of said gate array according to said information received.

9. A computing system comprising, in combination:

a plurality of dynamically configurable gate arrays each having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and Random Access Memory (RAM) programming means for programming said I/O blocks, said logic blocks and said routing resources, said RAM programming means defining an appropriate mode of operation for said gate array;

microprocessor means comprising a Reduced Instruction Set Computer (RISC) coupled to an external source and located within each of said gate arrays by programming said RAM programming means within said gate arrays for processing instructions received from said external source; and

reconfigurable instruction execution means coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks of said gate array according to said information received and implemented within each of said gate arrays by programming said RAM programming means within said gate arrays.

10. An integrated circuit computing device comprising, in combination:

a dynamically configurable gate array based on Random Access Memory (RAM), said gate array having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and Random Access Memory (RAM) programming means for programming said I/O blocks, said logic blocks and said routing resources, said RAM programming means defining an appropriate mode of operation for said gate array;

interface means implemented within said gate array for allowing communication between said gate array and an external device coupled to said interface means;

microprocessor means comprising a Reduced Instruction Set Computer (RISC) coupled to said interface means, and located within said gate array by programming said RAM programming means for processing instructions received from said external device; and

reconfigurable instruction execution means implemented within said gate array by programming said RAM programming means and coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external device and for performing manipulation and computation of data contained within said logic blocks of said gate array according to said information received.

11. A method of high-speed computing comprising the steps of:

providing a dynamically configurable gate array having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and programming means for programming said I/O blocks, said logic blocks, and said routing resources, said programming means defining an appropriate mode of operation for said gate array;

providing microprocessor means comprising a Reduced Instruction Set Computer (RISC) coupled to an external source and located within said gate array by programming said programming means for processing instructions received from said external source;

implementing reconfigurable instruction execution means within said gate array by programming said programming means, said reconfigurable instruction execution means being coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks of said gate array according to said information received; and

reconfiguring said reconfigurable instruction execution means by programming said programming means to change said reconfigurable instruction execution means so an operation on data within said reconfigurable instruction execution means is carried out by circuits within said gate array after said reconfiguring is complete.

12. The method of claim 11 wherein said microprocessor means remains unchanged when said reconfigurable instruction execution means is reconfigured by programming said programming means.

13. A computing system comprising, in combination:

a plurality of dynamically configurable gate arrays each having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and Random Access Memory (RAM) programming means for programming said I/O blocks, said logic blocks and said routing resources, said RAM programming means defining an appropriate mode of operation for said gate array;

microprocessor means coupled to an external source comprising a Reduced Instruction Set Computer (RISC) located within each of said gate arrays by programming said RAM programming means within said gate arrays for processing instructions received from said external source;

reconfigurable instruction execution means coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks and implemented within each of said gate arrays by programming said RAM programming means within said gate arrays according to said information received; and

host means coupled to said plurality of dynamically configurable gate arrays for programming a first of said plurality of dynamically configurable gate arrays to perform computations while said host means dynamically reconfigures a second of said plurality of dynamically configurable gate arrays.

14. A method of high-speed computing comprising the steps of:

providing a plurality of dynamically configurable gate arrays each having a plurality of input/output (I/O) pads, a plurality of I/O blocks, a plurality of programmable logic blocks, a plurality of programmable routing resources for interconnecting said I/O pads, said I/O blocks and said logic blocks, and programming means for programming said I/O blocks, said logic blocks, and said routing resources, said programming means defining an appropriate mode of operation for said gate array;

providing microprocessor means comprising a Reduced Instruction Set Computer (RISC) coupled to an external source and located within each of said gate arrays by programming said programming means for processing instructions received from said external source;

implementing reconfigurable instruction execution means within each of said gate arrays by programming said programming means, said reconfigurable instruction execution means being coupled to said microprocessor means for receiving and processing information received from at least one of said microprocessor means and said external source and for performing manipulation and computation of data contained within said logic blocks of said gate arrays according to said information received;

reconfiguring said reconfigurable instruction execution means by programming said programming means to change said reconfigurable instruction execution means so an operation on data within said reconfigurable instruction execution means is carried out by circuits within said gate arrays after said reconfiguring is complete; and

programming a first of said plurality of dynamically configurable gate arrays performing computations while said external source dynamically reconfigures a second of said plurality of dynamically configurable gate arrays.

15. The method of claim 14 wherein said I/O blocks comprise input means for providing a plurality of input signals to said logic blocks and said routing resources, and output means for providing a plurality of output signals from said logic blocks and said routing resources to said I/O blocks.

16. The method of claim 15 wherein said input means and said output means being implemented within said gate array by programming said programming means.

17. The method of claim 14 wherein said programming means comprises Random Access Memory (RAM) and wherein said programming means is programmed by writing data into said RAM.

18. The method of claim 17 wherein said RAM for said programming means comprises a shift register and wherein said programming means is programmed by shifting data into said shift register.