Integrated zener diode protection structures and fabrication methods for DMOS power devices

• US 5,602,046 A
• Filed: 04/12/1996
• Issued: 02/11/1997
• Est. Priority Date: 04/12/1996
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Calafut, Daniel, Sapp, Steven, Bencuya, Izak
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/631,080
• Time in Patent Office: 305 Days
• Field of Search: 437/41, 437/77, 437/149, 437/150, 148/DIG. 126, 148/DIG. 174
• US Class Current: 438/237
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/126 Power FETs
• CPC Class Codes: Y10S 148/174 Zener diodes
• CPC Class Codes: Y10S 438/983 Zener diodes

Abstract

In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The field plate creates a protection device similar to a zener diode, but exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the field plate length. The concentration gradients under the field plate, and hence the breakdown voltage, is controlled by suitable field plate length and other processing conditions. A zener breakdown programmability option is implemented so that the zener breakdown voltage is varied by suitable process selection using only one additional implant, temperature cycle, and photolithographic mask. The zener diode gate protection structure formed using the field plate has a high current per unit power; therefore, a smaller protection structure can be implemented compared to the prior art, because more current is conducted for a given size structure.

Claims

1. A method of fabricating an overvoltage protection device for an input of a semiconductor device, the method comprising the steps of:

growing a gate oxide layer on an underlying epitaxial layer of a first conductivity type;

forming a gate conductive layer on the gate oxide layer;

defining a first photolithographic mask over the gate conductive layer that protects a gate region and a field plate region;

etching the conductive layer through the first photolithographic mask so as to form a gate and a field plate;

implanting body impurities of a second conductivity type to form a transistor body implant region and an input pad body implant region;

removing the first photolithographic mask;

performing a thermal body drive-in step to diffuse the body impurities of the second conductivity type vertically and laterally to form a diffused transistor body region and a diffused input pad body implant region;

defining a second photolithographic mask that exposes a heavy body contact region within the diffused transistor body region;

implanting body contact impurities of the second conductivity type to form a heavy body implant region;

removing the second photolithographic mask;

performing a thermal body contact drive-in step to diffuse the body contact impurities of the second conductivity type vertically and laterally to form a diffused heavy body region;

defining a third photolithographic mask that exposes a source region within the diffused transistor body region and a zener diode cathode region within the diffused input pad body region;

implanting source impurities of the first conductivity type to form a source implant region and a zener cathode implant region;

removing the third photolithographic mask;

performing a thermal source drive-in step to diffuse the source impurities of the first conductivity type vertically and laterally to form a diffused source region and a diffused zener cathode region;

depositing an insulation layer;

defining a fourth photolithographic mask that protects the gate and a portion of the field plate and exposes portions of the diffused source region and the diffused zener cathode region;

etching the insulation layer through the fourth photolithographic mask;

depositing a metal layer;

defining a fifth photolithographic mask that protects an input pad metal region and a source metal region and exposes a region overlying the field plate; and

etching the metal layer through the fifth photolithographic mask.

2. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 1, further comprising the step of:

depositing a passivation layer.

3. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 1, wherein the first conductivity type is N type and the second conductivity type is P type.

4. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 3, further comprising the step of:

prior to the step of growing a gate oxide layer, growing the epitaxial layer on a heavily-doped substrate of the first conductivity type.

5. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 4, wherein the input is a gate input of a DMOS device.

6. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 5, wherein the gate oxide layer is approximately 400 Angstroms in thickness.

7. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 6, wherein the gate conductive layer is polysilicon.

8. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 7, wherein the gate conductive layer is approximately 5,500 Angstroms in thickness.

9. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 1, wherein the gate oxide layer is silicon dioxide.

10. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 3,

wherein the body impurities and the body contact impurities are boron atoms, and

wherein the source impurities are arsenic atoms.

11. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 10,

wherein the insulation layer is borophosphosilicate glass or phosphosilicate glass.

12. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 5, wherein the fourth photolithographic mask protects the entire field plate.

13. A method of fabricating an overvoltage protection device for an input of a semiconductor device, the method comprising the steps of:

growing a gate oxide layer on an underlying epitaxial layer of a first conductivity type;

forming a gate conductive layer on the gate oxide layer;

defining a first field plate photolithographic mask over the gate conductive layer that protects a field plate region;

etching the conductive layer through the first field plate photolithographic mask so as to form a field plate;

implanting body impurities of a second conductivity type to form an input pad body implant region;

removing the first field plate photolithographic mask;

performing a thermal zener drive-in step to diffuse the body impurities of the second conductivity type vertically and laterally to form a diffused input pad body implant region;

defining a first gate photolithographic mask over the gate conductive layer that protects a gate region;

etching the conductive layer through the first gate photolithographic mask so as to form a gate;

implanting body impurities of a second conductivity type to form a transistor body implant region;

removing the first gate photolithographic mask;

performing a thermal body drive-in step to diffuse the body impurities of the second conductivity type vertically and laterally to form a diffused transistor body region;

defining a second photolithographic mask that exposes a heavy body contact region within the diffused transistor body region;

implanting body contact impurities of the second conductivity type to form a heavy body implant region;

removing the second photolithographic mask;

performing a thermal body contact drive-in step to diffuse the body contact impurities of the second conductivity type vertically and laterally to form a diffused heavy body region;

defining a third photolithographic mask that exposes a source region within the diffused transistor body region and a zener diode cathode region within the diffused input pad body region;

implanting source impurities of the first conductivity type to form a source implant region and a zener cathode implant region;

removing the third photolithographic mask;

performing a thermal source drive-in step to diffuse the source impurities of the first conductivity type vertically and laterally to form a diffused source region and a diffused zener cathode region;

depositing an insulation layer;

defining a fourth photolithographic mask that protects the gate and portion of the field plate and exposes portions of the diffused source region and the diffused zener cathode region;

etching the insulation layer through the fourth photolithographic mask;

depositing a metal layer;

defining a fifth photolithographic mask that protects an input pad metal region and a source metal region and exposes a region overlying the field plate; and

etching the metal layer through the fifth photolithographic mask.

14. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 13, further comprising the step of:

depositing a passivation layer.

15. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 13, wherein the first conductivity type is N type and the second conductivity type is P type.

16. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 15, further comprising the step of:

prior to the step of growing a gate oxide layer, growing the epitaxial layer on a heavily-doped substrate of the first conductivity type.

17. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 16, wherein the input is a gate input of a DMOS device.

18. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 17, wherein the gate oxide layer is approximately 400 Angstroms in thickness.

19. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 18, wherein the gate conductive layer is polysilicon.

20. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 19, wherein the gate conductive layer is approximately 5,500 Angstroms in thickness.

21. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 13, wherein the gate oxide layer is silicon dioxide.

22. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 15,

wherein the body impurities and the body contact impurities are boron atoms, and

wherein the source impurities are arsenic atoms.

23. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 22,

wherein the insulation layer is borophosphosilicate glass or phosphosilicate glass.

24. A method of fabricating an overvoltage protection device for an input of a semiconductor device as in claim 17, wherein the fourth photolithographic mask protects the entire field plate.