Semiconductor device and method for manufacturing same

• US 5,602,059 A
• Filed: 09/08/1995
• Issued: 02/11/1997
• Est. Priority Date: 09/08/1994
• Status: Expired due to Fees

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Horiuchi, Michio, Harayama, Yoichi
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/525,078
• Time in Patent Office: 522 Days
• Field of Search: 437/209, 437/211, 437/214, 437/217, 437/218, 437/219, 437/220
• US Class Current: 438/15
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73269 Layer and TAB connectors
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

A semiconductor device includes a flat package substrate having a main surface on which is defined a semiconductor chip mount surface portion and onto which a semiconductor chip is to be mounted and a peripheral surface portion surrounding the semiconductor chip mount surface portion. An electrically insulating elastic layer is provided on the peripheral surface portion of the flat package substrate and a wiring pattern film is provided on an exposed main surface of the elastic layer. The wiring pattern film includes a base insulting film and wiring patterns which are formed on the base insulation film, each wiring pattern having a first end connected to an external connection terminal and a second end connected to the semiconductor chip. The semiconductor chip is sealed with a resin by potting.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

defining, on a main surface of a flat package substrate, a semiconductor chip mount portion having a periphery and a peripheral surface portion of the main surface extending about and outwardly from the periphery of the semiconductor chip mount portion;

joining an elastic layer to the peripheral surface portion of the main surface of the flat package substrate, said elastic layer having a thickness larger than a thickness of a semiconductor chip to be mounted on the semiconductor chip mount portion and having an inner wall surrounding, and at least in part defining, a cavity encompassing the semiconductor chip mount portion;

joining a wiring pattern film, having wiring patterns for connection with said semiconductor chip, to an exposed surface of said elastic layer;

positioning a semiconductor chip within said cavity and joining a back surface of said semiconductor chip to the semiconductor chip mount portion of the main surface of the flat package substrate;

sealing said semiconductor chip within said semiconductor device by potting same in a potting material; and

joining external connection terminals to respective ends of said wiring patterns on the wiring pattern film.

2. A method of manufacturing a semiconductor device as set forth in claim 1, further comprising the steps of:

forming joint holes and a device hole in an insulating base film of the wiring pattern film;

forming wiring patterns on said base film in such a manner that a first end of each wiring pattern is exposed at a respective joint hole and a second end thereof extends into said device hole of the wiring pattern film; and

joining a surface of said wiring pattern film, on which the wiring pattern is formed, to the exposed surface of the elastic layer.

3. A method of manufacturing a semiconductor device as set forth in claim 1, further comprising the steps of:

forming joint holes in an insulating base film of the wiring pattern film;

forming wiring patterns on the base film in such a manner that a first end of each wiring pattern is exposed in a respective joint hole and a second end thereof is connected to the semiconductor chip connecting portion of the wiring pattern film; and

joining a surface of said wiring pattern film, on which the wiring pattern is formed, to the exposed surface of the elastic layer.

4. A method of manufacturing a semiconductor device comprising the steps of:

mounting a semiconductor chip on a wiring pattern film having wiring patterns thereon so that the semiconductor chip is electrically connected to the wiring patterns;

conducting a test of the wiring pattern film, on which the semiconductor chip is mounted, to determine whether the semiconductor chip is acceptable or unacceptable;

joining an elastic layer to the peripheral surface portion of the main surface of the flat package substrate, said elastic layer having a thickness larger than a thickness of a semiconductor chip to be mounted on the semiconductor chip mount portion and having an inner wall surrounding, and at least in part defining, a cavity encompassing the semiconductor chip mount portion;

selecting a wiring pattern film associated with, and having the wiring patterns thereof connected to, an acceptable semiconductor chip, and joining the selected wiring pattern film to the exposed surface of said elastic layer;

positioning said semiconductor chip within said cavity and joining a back surface of said semiconductor chip to the semiconductor chip mount portion of the main surface of the flat package substrate;

sealing said semiconductor chip within said semiconductor device by potting same in a potting material; and

joining external connection terminals to respective first ends of said wiring pattern on the wiring pattern film.

5. A method of manufacturing a semiconductor device, comprising the steps of:

preparing an elastic layer and a wiring pattern film, the elastic layer having a thickness larger than a thickness of a semiconductor chip and the wiring pattern film comprising an insulating base film having first and second main surfaces and wiring patterns formed on the first main surface of the insulating base film;

joining the elastic layer to the first main surface of the insulating base film of the wiring pattern film, the elastic layer having an inner wall surrounding, and thereby defining, a cavity and an exposed main surface;

providing a flat package substrate having a main surface on which is defined a semiconductor chip mount portion and a peripheral surface portion surrounding the semiconductor chip mount portion;

joining the elastic layer to the peripheral surface portion of the main surface of said flat package substrate and such that the cavity therein surrounds and extends peripherally about the semiconductor chip mount portion of said main surface of said flat package substrate;

positioning a semiconductor chip within the cavity and joining a back surface of the semiconductor chip to the main surface of the flat package substrate, within the cavity;

sealing said semiconductor chip by potting; and

joining external connection terminals to respective ends of the wiring patterns of the wiring pattern film.

6. A method of manufacturing a semiconductor device as set forth in claim 5, further comprising the steps of:

forming joint holes and a device hole in the insulating base film of the wiring pattern film;

forming the wiring patterns on said insulating base film in such a manner that a first end of each wiring pattern is exposed at a respective joint hole and a second end thereof extends into said device hole of the wiring pattern film; and

joining the first main surface of the insulating base film, of said wiring pattern film and on which the wiring pattern is formed, to the exposed main surface of the elastic layer.

7. A method of manufacturing a semiconductor device as set forth in claim 5, further comprising the steps of:

forming joint holes on an insulating base film of the wiring pattern film;

forming wiring patterns on the insulating base film in such a manner that a first end of each wiring pattern is exposed in a respective joint hole and a second end thereof is connected to the semiconductor chip connecting portion of the wiring pattern film; and

joining a surface of the wiring pattern film, on which the wiring pattern is formed, to the exposed main surface of the elastic layer.

8. A method of manufacturing a semiconductor device, comprising the steps of:

mounting a semiconductor chip on a wiring pattern film, having wiring patterns thereon, so that the semiconductor chip is electrically connected to the wiring patterns;

conducting a test of the wiring pattern film, on which the semiconductor chip is mounted, to determine whether the semiconductor chip is acceptable or unacceptable;

joining an elastic layer to a surface of the wiring pattern film on which said wiring patterns are formed, the elastic layer having a thickness larger than a thickness of the semiconductor chip and an inner wall surrounding, and at least in part defining, a cavity;

defining, on a main surface of a flat package substrate, a semiconductor chip mount portion, having a periphery, and a peripheral surface portion on the main surface extending about and outwardly from the periphery of the semiconductor chip mount portion;

joining the elastic layer to the peripheral surface portion of the main surface of the flat package substrate and with the cavity therein surrounding the semiconductor chip mount portion of the flat package substrate;

positioning the semiconductor chip within the cavity and joining a back surface of the semiconductor chip to the semiconductor chip mount portion of the main surface of the flat package substrate;

sealing said semiconductor chip by potting; and

joining external connection terminals to respective first ends of the wiring patterns on the wiring pattern film.