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MOS operational transconductance amplifier using an adaptively-biased differential pair

  • US 5,602,509 A
  • Filed: 06/08/1995
  • Issued: 02/11/1997
  • Est. Priority Date: 06/09/1994
  • Status: Expired due to Fees
First Claim
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1. A MOS operational transconductance amplifier comprising:

  • (a) a differential pair of first and second MOSFETs whose sources are coupled together, said differential pair being driven by its tail current;

    (b) a quadritail circuit whose output current has a square-law characteristic;

    (c) a first current adjusting circuit for producing a first relationship between said tail current of said differential pair and said output current of said quadritail circuit;

    (d) a constant current source or sink;

    (e) said quadritail circuit comprising a first transistor pair of third and fourth MOSFETs, a second transistor pair of fifth and sixth MOSFETs, said quadritail circuit driven by a quadritail driving current;

    sources of said third, fourth, fifth and sixth MOSFETs being coupled together to be driven by said quadritail driving current;

    drains of said third and fourth MOSFETs of said first transistor pair being coupled together;

    drains of said fifth and sixth MOSFETs of said second transistor pair being coupled together;

    said output current of said quadritail circuit being derived from one of said coupled drains of said third and fourth MOSFETs and said coupled drains of said fifth and sixth MOSFETs;

    gates of said third and fourth MOSFETs being applied with a differential input signal; and

    gates of said fifth and sixth MOSFETs being coupled together and applied with a voltage divided component of said differential input signal;

    (f) a second current adjusting circuit for producing a second relationship between the current produced by said constant current source or sink and said quadritail driving current;

    said second current adjusting circuit also producing a third relationship between said current produced by said constant current source or sink and said tail current of said differential pair;

    (g) said differential input signal being applied across gates of said first and second MOSFETs;

    (h) a differential output signal being derived from drains of said first and second MOSFETs; and

    (i) a transconductance nonlinearity of said differential pair being compensated by said output signal of said quadritail circuit.

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