Non-Volatile, static random access memory with current limiting

• US 5,602,776 A
• Filed: 10/27/1995
• Issued: 02/11/1997
• Est. Priority Date: 10/17/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Weiner, Albert S., Herdt, Christian E.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/549,483
• Time in Patent Office: 473 Days
• Field of Search: 365/185, 365/154, 365/156, 365/185.05, 365/185.08, 371/66
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

The present invention provides a non-volatile, static random access memory (nvSRAM) cell with a current limiting feature that prevents current that is provided to the cell or array of cells during a recall operation in which information is transferred from the non-volatile portion of the cell or array to the static random access memory portion of the cell or array from reaching a point that would be detrimental to the cell or array. The current limiting device is located between the nvSRAM cell or array of cells and ground. In one embodiment, the current limiting device includes a variable resistance and a device for modulating the resistance so that the resistance is high at the beginning of a recall operation and decreases thereafter.

Claims

1. A non-volatile, static random access memory device with improved current limiting, comprising:

a memory cell comprised of a static random access memory for retaining a bit of data that, if power is removed therefrom, can be lost, and a non-volatile memory that is capable of retaining said bit of data even after power has been removed from said memory cell;

first means for use in transferring a bit of data between said memory cell and an exterior environment;

second means, extending from said static random access memory to said non-volatile memory, for use in transferring a bit of data from said static random access memory to said non-volatile memory and from said non-volatile memory to said static random access memory;

third means for operatively connecting said memory cell to a control means for controlling transfer of a bit of data between said static random access memory and said non-volatile memory;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground, wherein said means for operatively connecting said memory cell to the ground is different from said first, second and third means; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell.

2. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said means for limiting current includes a resistor.

3. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said means for limiting current includes a variable resistor.

4. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said means for limiting current includes a variable resistor and means for changing the resistance provided by said variable resistor.

6. A non-volatile, static random access memory device, as claimed in claim 1, wherein:

said means for limiting current includes a transistor.

5. A non-volatile, static random access memory device with improved current limiting, comprising:

a memory cell comprised of a static random access memory for retaining a bit of data that, if power is removed therefrom, can be lost, and a non-volatile memory that is capable of retaining said bit of data even after power has been removed from said memory cell;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said means for limiting current includes a variable resistor and means for changing the resistance provided by said variable resistor so that the resistance is relatively high at the beginning of a recall operation and relatively low at the end of the recall operation.

7. A non-volatile, static random access memory device with improved current limiting, comprising:

a memory cell comprised of a static random access memory for retaining a bit of data that, if power is removed therefrom, can be lost, and a non-volatile memory that is capable of retaining said bit of data even after power has been removed from said memory cell;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said means for limiting current includes a transistor and means for varying the resistance provided by said transistor.

8. A non-volatile, static random access memory device with improved current limiting, comprising:

a memory cell comprised of a static random access memory for retaining a bit of data that, if power is removed therefrom, can be lost, and a non-volatile memory that is capable of retaining said bit of data even after power has been removed from said memory cell;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said means for limiting current includes a transistor and means for varying the resistance provided by said transistor so that said resistance is relatively high at the beginning of a recall operation and relatively low at the end of said recall operation.

9. A non-volatile static random access memory device with improved current limiting, comprising:

a memory cell comprised of a static random access memory for retaining a bit of data that, if power is removed therefrom, can be lost, and a non-volatile memory that is capable of retaining said bit of data even after power has been removed from said memory cell;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said memory cell includes means for providing a pull-up resistance;

wherein said means for limiting current includes a variable resistor and means for changing the resistance provided by said variable resistor so that the resistance provided by said variable resistor is relatively high at the beginning of a recall operation and decreases thereafter.

10. A non-volatile, static random access memory device, as claimed in claim 9, further comprising:

means for increasing a voltage applied to said means for providing a pull-up resistance as the resistance of said variable resistor is decreased to provide sensitivity.

11. A non-volatile, static random access memory device with current limiting, comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein said bit of data can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving said bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to receive said bit of data from said static random access memory constitutes a store operation;

wherein the capability of said non-volatile memory to transmit said bit of data back to said static random access memory constitutes a recall operation;

first means for use in transferring said bit of data from said memory cell to an exterior environment;

second means, extending from said static random access memory to said non-volatile memory, for use in transferring said bit of data from said static random access memory to said non-volatile memory and from said non-volatile memory to said static random access memory

third means for operatively connecting said memory cell to a control means for effecting store and recall operations;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground, wherein said means for operatively connecting said memory cell to the ground is different from said first, second and third means; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell.

12. A non-volatile, static random access memory device with current limiting, comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein said bit of data can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving said bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to receive said bit of data from said static random access memory constitutes a store operation;

wherein the capability of said non-volatile memory to transmit said bit of data back to said static random access memory constitutes a recall operation;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said non-volatile memory differentially stores said bit of data in a first semiconductor device with a first threshold that, if exceeded, causes said first semiconductor device to conduct current and in a second semiconductor device with a second threshold that is different than said first threshold and, if exceeded, causes said second semiconductor device to conduct current;

wherein said first and second thresholds are established so that at least one of said first and second semiconductor devices conduct current during said recall operation.

13. A non-volatile, static random access memory device with current limiting, comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein said bit of data can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving said bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to receive said bit of data from said static random access memory constitutes a store operation;

wherein the capability of said non-volatile memory to transmit said bit of data back to said static random access memory constitutes a recall operation;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said non-volatile memory differentially stores said bit of data in a first semiconductor device with a first threshold that, if exceeded, causes said first semiconductor device to conduct current and in a second semiconductor device with a second threshold that is different than said first threshold and, if exceeded, causes said second semiconductor device to conduct current;

wherein said first threshold is susceptible to decay and if said first threshold decays beyond a first limit, said recall operation is not possible;

wherein said second threshold is also susceptible to decay and if said second threshold decays beyond a second limit, said recall operation is not possible;

wherein said first limit is located between said second threshold and said second limit.

14. A non-volatile, static random access memory device with current limiting, comprising:

a memory cell comprising;

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data to the exterior environment;

wherein said bit of data can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that is capable of receiving said bit of data from said static random access memory prior to the possible removal of power from said memory cell, retaining said bit of data even after removal of power from said memory cell, and transmitting said bit of data back to said static random access memory when power is being provided to said memory cell;

wherein the capability of said non-volatile memory to receive said bit of data from said static random access memory constitutes a store operation;

wherein the capability of said non-volatile memory to transmit said bit of data back to said static random access memory constitutes a recall operation;

means for operatively connecting said memory cell to a power supply;

means for operatively connecting said memory cell to a ground; and

means, located between said memory cell and said means for operatively connecting said memory cell to the ground, for limiting the current to be provided by the power supply to said memory cell;

wherein said non-volatile memory differentially stores said bit of data in a first semiconductor device with a first threshold that, if exceeded, causes said first semiconductor device to conduct current and a second semiconductor device with a second threshold that is different than said first threshold and, if exceeded, causes said second semiconductor device to conduct current;

wherein said first threshold is susceptible to decay and if said first threshold decays beyond a first limit, said recall operation is not possible;

wherein said second threshold is also susceptible to decay and if said second threshold decays beyond a second limit, said recall operation is not possible;

wherein at least one of said first limit and said second limit is variable.

15. A non-volatile, static random access memory array with improved current limiting, comprising:

a first memory cell comprised of a first static random access memory for communicating a first bit of data with an exterior environment in an SRAM operation and retaining said first bit of data, wherein said first static random access memory is capable of losing said bit of data if power is removed therefrom, said first memory cell further comprised of a first non-volatile memory that is capable of communicating said first bit of data with said first static random access memory in a store or recall operation, wherein said first non-volatile memory is capable of retaining said first bit of data even after power has been removed from said first memory cell;

first means for operatively connecting said first memory cell to a power supply;

first means for operatively connecting said first memory cell to a ground;

a first resistor means, located between said first memory cell and said first means for operatively connecting said first memory cell to ground, for limiting the current to be provided by the power supply to said first memory cell during a recall operation;

a second memory cell comprised of a second static random access memory for communicating a second bit of data with an exterior environment in an SRAM operation and retaining said second bit of data, wherein said second static random access memory is capable of losing said bit of data if power is removed therefrom, said second memory cell further comprised of a second non-volatile memory that is capable of communicating said second bit of data with said second static random access memory in a store or recall operation, wherein said second non-volatile memory is capable of retaining said second bit of data even after power has been removed from said second memory cell;

second means for operatively connecting said second memory cell to a power supply;

second means for operatively connecting said second memory cell to a ground;

a second resistor means, located between said second memory cell and said second means for operatively connecting said second memory cell to ground, for limiting the current to be provided by the power supply to said second memory cell during a recall operation; and

means for connecting said first resistor in parallel with said second resistor to provide a reduced resistance to said first memory cell during an SRAM operation in said first memory cell.

16. A non-volatile, static random access memory array, as claimed in claim 15, wherein:

said first resistor means includes a first variable resistor; and

said second resistor means includes a second variable resistor.

17. A non-volatile, static random access memory array, as claimed in claim 16, further comprising:

means for controlling said first and said second variable resistors so that each provides a high resistance during a recall operation and a low resistance during an SRAM operation.

18. A non-volatile, static random access memory array, as claimed in claim 15, further comprising:

a third memory cell comprised of a third static random access memory and a third non-volatile memory as set forth with respect to said first memory cell; and

third means for operatively connecting said third memory cell to a power supply;

wherein said first resistor means is operatively connected to said third memory cell.