Semiconductor memory device having floating gate transistors and data holding means

• US 5,602,777 A
• Filed: 05/24/1995
• Issued: 02/11/1997
• Est. Priority Date: 09/28/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ueno, Shounosuke, Nawaki, Masaru
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/449,022
• Time in Patent Office: 629 Days
• Field of Search: 365/185.07, 365/185.09, 365/185.18, 365/185.21, 365/185.24, 365/49
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

In a semiconductor memory device, a data holding unit is disposed separately from the first and second floating gate transistors. A voltage difference is generated by the difference between the threshold voltages of the first and second floating gate transistors, and the voltage difference is stored in the form of a binary data. Thereafter, the first and second floating gate transistors are turned off. Thus, a minute current which always flows through the first and second floating gate transistors in the conventional technique is prevented from being generated so that the power consumption is reduced. In addition, data is fetched from the data holding unit while the bias voltage generating units are turned off. Thus, the time period of operating the bias voltage generating units is eliminated so that the memory device can operate at a high speed.

Claims

1. A semiconductor memory device comprising:

a first floating gate transistor and a second floating gate transistor each storing charges, the amount of the charges stored in the first floating gate transistor being made different from that stored in the second floating gate transistor;

at least one control means for generating a voltage difference in accordance with respective threshold voltages of the first and second floating gate transistors, and for then turning off the first and second floating gate transistors; and

at least one data holding means for holding the voltage difference as a binary data

and wherein the control means detects completion of sensing operation of the data holding means, and turns off the first and second floating gate transistors after the detection.

2. A semiconductor memory device according to claim 1,

wherein the control means further comprises at least one switching device provided as corresponding to each of the data holding means, the switching device being connected to a line pulled up to a first potential level, the switching device pulling down the potential level of the line to a second potential level, and

wherein the control means drives the switching device using an output of the detection indicative of the voltage difference between the respective threshold voltages of the first and second floating gate transistors, and detects the completion of the sensing operation of the data holding means by detecting that each of the switching devices have been driven.

3. A semiconductor memory device according to claim 1, wherein the control means further comprises:

a first bias voltage generating means for supplying a bias voltage to a gate of each of the first and second floating gate transistors;

a first transistor of a first conductive type connected upstream to the first floating gate transistor in series;

a second transistor of the first conductive type connected upstream to the second floating gate transistor in series;

a second bias voltage generating means for supplying a bias voltage to a gate of each of the first and second transistors of the first conductive type,

and wherein the first and second transistors of the first conductive type are turned off, thereby turning off the first and second floating gate transistors.

4. A semiconductor memory device according to claim 3,

wherein the data holding means is connected between a first potential level and a second potential level via a switching transistor,

wherein the first floating gate transistor is connected to the data holding means via the first transistor of the first conductive type,

wherein the second floating gate transistor is connected to the data holding means via the second transistor of the first conductive type, and

wherein the control means, when difference between the first and second potential levels changes beyond a predetermined extent, turns on the first and second transistors of the first conductive type so as to supply a current to the first and the second floating gate transistors, and thereafter turns on the switching transistor so as to turn off the first and second transistor of the first conductive type in a synchronizing manner with decreasing of a drain voltage of either the first and second transistors of the first conductive type to a prescribed intermediate level between the first and second potential levels.

5. A semiconductor memory device according to claim 4, wherein the data holding means further comprises:

a series circuit of a first transistor of a second conductive type and a third transistor of the first conductive type;

a parallel circuit of a second transistor of the second conductive type and a fourth transistor of the first conductive type,

wherein a gate of the first transistor of the second conductive type and a gate of the third transistor of the first conductive type are connected to a junction between the second transistor of the second conductive type and the fourth transistor of the first conductive type,

wherein a gate of the second transistor of the second conductive type and a gate of the fourth transistor of the first conductive type are connected to a junction between the first transistor of the second conductive type and the third transistor of the first conductive type, and

wherein a voltage is applied to the first and second transistors of the second conductive type.