Flash EEprom system

• US 5,602,987 A
• Filed: 12/29/1993
• Issued: 02/11/1997
• Est. Priority Date: 04/13/1989
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): HUA, LY
• Application Number:
  US08/174,768
• Time in Patent Office: 1,140 Days
• Field of Search: 371/10.2, 371/10.3, 371/40.1, 365/200, 365/185.09, 365/201, 365/189.07, 395/575, 395/182.03, 395/182.04, 395/182.05, 395/182.06, 395/427, 395/430
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:

providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,

partitioning the memory cells within the individual sectors into at least a user data portion and an overhead portion,

detecting a predefined condition when individual sectors become unusable and linking the addresses of such unusable sectors with addresses of other sectors that are useable,

causing the controller, in response to receipt from the processor of an address in a format designating at least one magnetic disk sector, to generate an address of a non-volatile memory sector that corresponds to said at least one magnetic disk sector,

accessing a usable sector of the memory system, if the sector with the generated address is unusable, by referring to the linked address of another sector that is usable and then accessing that other sector,

either writing data to, or reading data from, the user data portion of the accessed usable sector, and

either writing to, or reading from, said overhead portion of the accessed usable sector, information related to either the accessed usable sector or data stored in the user data portion of said accessed useful sector.

2. The method according to claim 1, wherein the detecting of the predefined condition includes detecting when individual sectors become defective.

3. The method according to claim 2, wherein the detecting of when individual sectors become defective includes determining when a number of individual defective memory cells within a sector exceed a given number.

4. The method according to claim 1, wherein the user data portion of the individual non-volatile memory sectors has a capacity of substantially 512 bytes.

5. The method according to claim 1, wherein the information stored in the overhead portion of the individual sectors includes an address of the respective ones of the individual sectors.

6. The method according to claim 1, wherein the information stored in the overhead portion of the individual sectors includes an error correction code calculated from data stored in the user data portions of corresponding ones of the individual sectors.

7. The method according to claim 1 wherein linking the address of unusable sectors with sectors that are useable includes maintaining a list within the card that links such unusable sectors with addresses of corresponding ones of the other sectors that are useable, and wherein accessing a usable sector includes referring to the list to translate the address of the unusable sector into an address of a usable sector.

8. The method according to claim 1 wherein linking the address of such unusable sectors includes storing within individual ones of the defective sectors addresses of corresponding useable sectors, and wherein accessing a usable sector corresponding to an unusable sector includes referring to the useable sector address stored in the unusable sector.

9. The method according to claim 1, wherein causing the controller to generate an address of a non-volatile memory sector includes doing so for a non-volatile memory sector that corresponds to only one magnetic disk sector, wherein the user data portion of the individual non-volatile memory sectors has a capacity that is substantially the same as a user data portion of said one magnetic disk sector.

10. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:

providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,

partitioning the memory cells within the individual sectors into at least a user data portion and an overhead portion,

causing the controller, in response to receipt from the processor of an address in a format designating at least one magnetic disk sector, to designate an address of at least one non-volatile memory sector that corresponds with said at least one magnetic disk sector,

either writing user data to, or reading user data from, the user data portion of said at least one non-volatile memory sector, and

either writing to, or reading from, said overhead portion of said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to data stored in the user data portion of said at least one non-volatile memory sector.

11. The method of claim 10, wherein the user data portion of the individual sectors has a capacity of substantially 512 bytes.

12. The method of claim 10, wherein the overhead data stored in said overhead portion of the individual sectors includes addresses of the individual sectors.

13. The method of claim 10, wherein partitioning the memory cells includes partitioning said memory cells within the individual sectors to include an additional portion of spare memory cells.

14. The method of claim 13, wherein the overhead data stored in said overhead portion of the individual sectors includes an identification of any defective cells within the user data portion of corresponding ones of said sectors, said method additionally comprising causing the controller to read the identification of defective cells from the overhead portion of said addressed at least one non-volatile memory sector and then to substitute therefore other cells within the spare cell portion of the addressed at least one non-volatile memory sector.

15. The method of claim 10, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory sectors within the array, and, wherein designating an address of a sector includes, in response to designating an address of a defective sector, substituting an address of another sector instead.

16. The method of claim 10, wherein the individual sectors include only one user data portion and only one overhead data portion.

17. A memory system on a card that is connectable to a host computer system, said memory system comprising:

an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said memory cells that are erasable together as a unit, the individual sectors having enough cells for storing a given amount of user data and overhead data, and

means connectable to said computer system for controlling operation of the array, said controlling means including;

means responsive to receipt of a magnetic disk sector address from the host computer system for addressing a corresponding non-volatile memory sector,

means for reading the overhead data stored in the addressed sector prior to either reading the user data from, or writing user data to, the addressed sector, and

means responsive to the read overhead data for executing an instruction from the host computer system to perform a designated one of reading user data from, or writing user data to, the addressed sector.

18. The memory system according to claim 17 wherein said controlling means additionally includes means listing any unusable ones of said plurality of non-volatile memory sectors for linking said unusable sectors with others of said sectors that are usable, and wherein said non-volatile memory sector addressing means includes means for accessing linked others of said sectors in place of said unusable sectors.

19. The memory system according to claim 17 wherein said given amount of user data is substantially 512 bytes.

20. The memory system according to claim 17 wherein said magnetic disk sector address includes a head, cylinder and sector.

21. The memory system according to claim 17 wherein the individual sectors of the memory array additionally have enough cells for providing redundant cells in excess of that necessary to store said given amount of user data and said overhead data, said controlling means additionally including means for substituting redundant cells of a sector for any defective cells within the sector.

22. The memory system according to claim 21 wherein said substituting means including means referencing the overhead data of an addressed sector for substituting redundant cells within the addressed sector.

23. A memory system having electrical terminations for establishing a connection with a host computer system, said memory system comprising:

an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said memory cells that are erasable together as a unit, the individual sectors having enough cells for storing a given amount of user data and some overhead data, and

a memory controller connected between said electrical terminations and said memory cell array for controlling operation of the array, said controller including;

means responsive to receipt of one or more mass memory storage block addresses through said terminations for addressing one or more of the non-volatile memory sectors, said addressing means including means responsive to an identification of any of the non-volatile memory sectors that are unusable for substituting another usable sector therefor,

means for reading overhead data stored in the addressed sector prior to either reading the user data from, or writing User data to, the addressed sector, and

means responsive to the read overhead data for either reading user data from, or writing user data to, the addressed sector.

24. The memory system according to claim 23 wherein the identification of any unusable sectors includes a list maintained within the memory system unit that links addresses of unusable sectors with corresponding usable sectors.

25. The memory system according to claim 23 wherein the identification of any unusable sectors includes a record of individual addresses of substitute usable sectors stored as part of the overhead data in respective ones of the unusable sectors.

26. The memory system according to any one of claims 23-25 wherein the identification of any unusable sectors includes inoperable or defective sectors.

27. The memory system according to any one of claims 23-25 wherein the identification of any unusable sectors includes sectors that contain a number of defective cells in excess of a preset number.

28. The memory system according to any one of claims 23-25 wherein said given amount of user data is substantially equal to 512 bytes.

29. The memory system according to any one of claims 23-25 wherein said controller additionally includes means for selecting a plurality of sectors for an erase operation, and means for simultaneously performing an erase operation on only the selected plurality of sectors.

30. The memory system according to claim 23 wherein said individual non-volatile memory sectors additionally have redundant memory cells in excess of that necessary to store said given amount of user data and said overhead data, said controller additionally including means for substituting redundant memory cells of an individual sector for defective memory cells within the individual sector.

31. The memory system according to claim 23 wherein the overhead data reading means includes means for reading from the overhead data of an addressed sector an address of that sector, and wherein the controller additionally includes means for comparing the read overhead data address with the address of the sector, thereby to confirm that the desired sector has been addressed.

32. The memory system according to any one of claims 23-25, 30 and 31 wherein the given amount of user data that is storable in individual sectors is substantially equal to a size of individual mass memory storage blocks of the host computer system, and wherein the addressing means maps addresses of individual ones of the mass memory storage blocks into unique individual ones of the non-volatile memory sectors.

33. The memory system according to any one of claims 23-25, 30 and 31 wherein said memory system unit is implemented on a single printed circuit card.

34. The memory system according to any one of claims 23-25, 30 and 31 wherein the one or more mass memory storage block addresses to which the controller addressing means is responsive consists of one or more magnetic disk sector addresses.

35. In a computer system including a processor and a memory system, wherein the memory system includes an array of integrated electronic circuit non-volatile floating gate memory cells partitioned into a plurality of distinct sectors of said memory cells that are individually erasable together as a unit separately from other sectors, a method of operating the memory system, comprising:

removably connecting said memory system including a controller to the computer system in a manner that said controller communicates with said processor for controlling operation of the array,

in response to receipt from the processor of an address in a format designating at least one mass memory storage block, generating through the controller (1) an address of at least one of said plurality of sectors of non-volatile memory corresponding to said at least one mass memory storage block and (2) an erase, write or read command,

in response to an erase command, erasing said at least one sector,

in response to a write command, reading, from an overhead portion of said at least one sector, overhead data of a characteristic of said at least one sector, and thereafter writing user data in the user data portion of said at least one sector and writing a characteristic of the written user data in the overhead portion of said at least one sector, and

in response to a read command, reading, from an overhead portion of said at least one sector, overhead data of a characteristic of said at least one sector or of data stored in the user data portion of said at least one sector, and thereafter reading data from the user data portion of said at least one sector.

36. The method of claim 35, which additionally comprises storing within the memory system links from addresses of any unusable sectors to addresses of others of said plurality of sectors, and wherein generating an address of said at least one of said plurality of sectors includes referring to said address links to substitute an address of a useable sector for an address of an unusable sector.

37. The method of claim 36 the address links are stored for sectors that are unusable by reason of more that a predetermined number of memory cells therein being defective.

38. The method of claim 36 wherein any links to addresses of useable ones of said plurality of sectors are stored in the overhead portion of unusable ones of said plurality of sectors.

39. The method of claim 35 wherein erasing said at least one sector includes simultaneously erasing two or more but less than all of said plurality of sectors.

40. The method of claim 36 wherein generating an address of said at least one sector includes generating addresses of a number of said plurality of sectors that is equal to a number of mass memory storage block addresses received from the processor.

41. The method of claim 40, wherein the user data portion of the individual sectors has a capacity of substantially 512 bytes.

42. The method of claim 35, wherein the overhead data stored in said overhead data portion of said at least one sector includes the address of said at least one sector.

43. The method of claim 42, wherein, in response to either the write command or the read command, overhead data that is read includes the address of said at least one sector.

44. The method of claim 43, wherein the address read from the overhead portion of said at least one sector is compared with the address that was generated through the controller.

45. The method of claim 35, wherein the overhead data stored in said overhead data portion of said at least one sector includes, if said at least one sector is defective, an address linking said at least one sector to another of said plurality of sectors.

46. The method of claim 45, wherein generating an address of said at least one of said plurality of sectors includes referring to said address linking to substitute an address of a useable sector for an address of an unusable sector.

47. The method of claim 35, wherein the overhead data stored in said overhead portion of said at least one sector includes an identification of any defective cells within the user data portion of said at least one sector.

48. The method of claim 47, additionally comprising, in response to either the write command or the read command, reading through the controller the identification of defective cells from the overhead portion of said at least one sector and then substituting therefore other cells within the said at least one sector.

49. The method of claim 35, wherein the writing of a characteristic of the user data includes calculating an error correction code from the written user data and writing said error correction code into the overhead portion of said at least one sector.

50. The method of claim 35, wherein said at least one mass memory storage block sector address received from the processor includes a head, cylinder and sector.