Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit

• US 5,602,999 A
• Filed: 04/30/1990
• Issued: 02/11/1997
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/517,005
• Time in Patent Office: 2,479 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/400, 395/425, 395/550, 395/600, 395/800, 395/401, 365/189.01, 365/191, 365/194, 365/205, 365/222, 365/189.05
• US Class Current: 711/1
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/23094 Debounce key
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 : Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35381 : Convert in real time input peripheral data to processor data, ouput data format
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/35588 : Pack, compress data efficiently in memory
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36227 : Assist operator to calculate unknown points, contours
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36395 : Load local computer program from host, data transfer ram to rom, BTR
• CPC Class Codes: G05B 2219/36502 : Ram for variable servo data, rom for fixed servo routine
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36506 : Store in Rom and Ram
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 12/0215 : with look ahead addressing means
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G09G 5/18 : Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/0033 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03H 17/0291 : Digital and sampled data filters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Memory technologies for storing filter samples include RAMs and CCDs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Claims

1. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address having less significant bits and having more significant bits;

a read accessing circuit coupled to the memory, coupled to the address generator, and read accessing data stored by the memory in response to the address generated by the address generator;

a processor coupled to the read accessing circuit and processing data read accessed by the read accessing circuit;

a first detector circuit coupled to the address generator and generating a first detector signal in response to detection of a change in the more significant bits of the address generated by the address generator;

a second detector circuit coupled to the address generator and generating a second detector signal in response to detection of a change in the less significant bits of the address generated by the address generator; and

a delay circuit coupled to the first detector circuit, coupled to the second detector circuit, and delaying generating of the address by the address generator in response to the first detector signal and in response to the second detector signal.

2. A memory system as set forth in claim 1, wherein the memory is a dynamic random access memory storing the data to be processed in dynamic form and wherein the memory system further comprises:

a third detector circuit coupled to the processor and generating a third detector signal in response to detection of time available by the processor to refresh the dynamic random access memory; and

a refresh circuit coupled to the third detector circuit, coupled to the dynamic random access memory, and refreshing the data stored by the dynamic random access memory in response to the third detector signal.

3. A memory system as set forth in claim 1, wherein the first detector circuit includes a comparator circuit generating the first detector signal in response to detection of a change in the more significant bits of the address generated by the address generator by comparison of the present value of the more significant bits of the address and the prior value of the more significant bits of the address and wherein the second detector circuit includes a comparator circuit generating the second detector signal in response to detection of a change in the less significant bits of the address generated by the address generator by comparison of the present value of the less significant bits of the address and the prior value of the less significant bits of the address.

4. A memory system as set forth in claim 1, wherein the memory includes:

a refreshable memory circuit storing the data as dynamic data;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the refresh circuit, coupled to the read accessing circuit, and generating a refresh control signal in response to the read accessing of data by the read accessing circuit and in response to the refresh input signal to resolve contention between the read accessing of data by the read accessing circuit and the refresh input signal; and

a memory refresh circuit refreshing the dynamic data stored by the refreshable memory circuit in response to the refresh control signal.

5. A memory system as set forth in claim 1, wherein the memory includes:

a refreshable memory circuit storing the data as dynamic data;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the refresh circuit, coupled to the processor, and generating a refresh control signal in response to the processing of data by the processor and in response to the refresh input signal to resolve contention between the processing of data by the processor and refreshing of the data stored by the refreshable memory circuit; and

a memory refresh circuit refreshing the dynamic data stored by the refreshable memory circuit in response to the refresh control signal.

7. A memory system as set forth in claim 1, wherein the processor includes a display processor coupled to the accessing circuit and generating display data by processing the data accessed by the accessing circuit;

wherein the memory system further comprises a display monitor coupled to the display processor and displaying an image in response to the display data.

8. A memory system as set forth in claim 1, wherein the processor includes an image processor processing the data accessed by the accessing circuit to generate image display data;

wherein the memory system further comprises a display monitor coupled to the image processor and displaying an image in response to the image display data.

10. A memory system as set forth in claim 1, further comprising a read only memory storing a computer program;

wherein the processor includes a stored program computer coupled to the read only memory and processing the data read accessed by the accessing circuit in response to the program stored by the read only memory.

6. A memory system comprising:

a data memory storing data to be processed;

an address generator generating an address having less significant bits and having more significant bits;

a continuous output extended tristate read accessing circuit coupled to the data memory, coupled to the address generator, and generating continuously output read accessed data that is extended without tristate interruption during a plurality of read accessing operations;

a first detector circuit coupled to the address generator and generating a first detector signal in response to detection of a change in the more significant bits of the address generated by the address generator;

a second detector circuit coupled to the address generator and generating a second detector signal in response to detection of a change in the less significant bits of the address generated by the address generator;

a delay circuit coupled to the first detector circuit, coupled to the second detector circuit, and delaying generating of the address by the address generator in response to the first detector signal and in response to the second detector signal;

a program memory storing a computer program;

a stored program computer coupled to receive the computer program stored by the program memory and coupled to receive the continuously output read accessed data generated by the continuous output extended tristate read accessing circuit, the stored program computer generating processed output data by processing the received continuously output read accessed data in response to the received computer program; and

a write accessing circuit coupled to the data memory, coupled to receive the address generated by the address generator, and coupled to receive the processed output data generated by the stored program computer, the write accessing circuit writing the received processed output data into the data memory in response to the received address and in response to the received processed output data.

9. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address having less significant bits and having more significant bits;

a read accessing circuit coupled to the memory, coupled to the address generator, and read accessing data stored by the memory in response to the address generated by the address generator;

a processor coupled to the read accessing circuit, the processor being a television image processor processing the data read accessed by the read accessing circuit to generate television image data;

a first detector circuit coupled to the address generator and generating a first detector signal in response to detection of a change in the more significant bits of the address generated by the address generator;

a second detector circuit coupled to the address generator and generating a second detector signal in response to detection of a change in the less significant bits of the address generated by the address generator;

a delay circuit coupled to the first detector circuit, coupled to the second detector circuit, and delaying generating of the address by the address generator in response to the first detector signal and in response to the second detector signal; and

a television monitor coupled to the television image processor and displaying a television image in response to the television image data.

11. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating addresses;

a continuous output read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive addresses generated by the address generator, the continuous output read accessing circuit generating continuous output read accessed data by read accessing data stored by the dynamic random access memory in response to the received addresses, the continuous output read accessing circuit generating continuous output read accessed data during a plurality of read operations in response to the read accessing of data stored by the dynamic random access memory;

a processor coupled to receive continuous output read accessed data generated by the continuous output read accessing circuit and coupled to receive addresses generated by the address generator, the processor processing the received continuous output read accessed data generated by the continuous output read accessing circuit;

a detector circuit coupled to receive addresses generated by the address generator, the detector circuit generating a detector signal in response to detection of a change in a received address; and

a delaying circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the delaying circuit delaying generating of the addresses by the address generator in response to the received detector signal.

13. A memory system as set forth in claim 11, wherein the dynamic random access memory includes:

a dynamic random access memory circuit storing the data as dynamic data;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the refresh circuit, coupled to the processor, and generating a refresh control signal in response to the processing of data by the processor and in response to the refresh input signal to resolve contention between the processing of data by the processor and the refresh input signal; and

a memory refresh circuit refreshing the dynamic data stored by the dynamic random access memory circuit in response to the refresh control signal.

14. A memory system as set forth in claim 11, further comprising:

a program memory storing a computer program, wherein the processor includes a stored program computer coupled to the program memory and processing the continuous output read accessed data in response to the program stored by the program memory; and

a write accessing circuit coupled to the dynamic random access memory, coupled to the address generator, coupled to the stored program computer, and write accessing data into the dynamic random access memory in response to the addresses and in response to the processing of the continuously generated output read accessed data.

16. A memory system as set forth in claim 11, wherein the processor includes an artificial intelligence processor processing the continuous output read accessed data to generate artificial intelligence data.

17. A memory system as set forth in claim 11, wherein the processor includes an image processor processing the continuous output read accessed data to generate image display data;

the memory system further comprising a display monitor coupled to the image processor and displaying an image in response to the image display data.

18. A memory system as set forth in claim 11, wherein the processor includes a television image processor processing the continuous output read accessed data to generate television image data;

wherein the memory system further comprises a television monitor coupled to the television image processor and displaying a television image in response to the television image data.

19. A memory system as set forth in claim 11, further comprising a read only memory storing a computer program;

wherein the processor includes a stored program computer coupled to the read only memory and processing the continuous output read accessed data in response to the program stored by the read only memory.

20. A memory system as set forth in claim 11, further comprising:

an external scanout address update circuit coupled to the detector circuit and updating the addresses generated by the address generator at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the detector circuit and updating the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal.

12. A memory system comprising:

a dynamic random access memory storing data, the dynamic random access memory including a refreshable memory circuit storing the data as dynamic data;

an address generator generating addresses;

a continuous output read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive addresses generated by the address generator, the continuous output read accessing circuit generating continuous output read accessed data by read accessing data stored by the dynamic random access memory in response to the received addresses, the continuous output read accessing circuit generating continuous output read accessed data during a plurality of read operations in response to the read accessing of data stored by the dynamic random access memory;

a processor coupled to receive continuous output read accessed data generated by the continuous output read accessing circuit and coupled to receive addresses generated by the address generator, the processor processing the received continuous output read accessed data generated by the continuous output read accessing circuit;

a detector circuit coupled to receive addresses generated by the address generator, the detector circuit generating a detector signal in response to detection of a change in a received address;

a delaying circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the delaying circuit delaying generating of the addresses by the address generator in response to the received detector signal;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the processor, coupled to the refresh circuit, and generating a refresh control signal in response to the processing by the processor of data stored by the dynamic random access memory to resolve contention between the processing of the data by the processor and the refresh input signal; and

a memory refresh circuit refreshing the dynamic data stored by the refreshable memory circuit in response to the refresh control signal.

15. A memory system comprising

a dynamic random access memory storing data;

an address generator generating addresses;

a continuous output read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive addresses generated by the address generator, the continuous output read accessing circuit generating continuous output read accessed data by read accessing data stored by the dynamic random access memory in response to the received addresses, the continuous output read accessing circuit generating continuous output read accessed data during a plurality of read operations in response to the read accessing of data stored by the dynamic random access memory;

a processor coupled to receive continuous output read accessed data generated by the continuous output read accessing circuit and coupled to receive addresses generated by the address generator, the processor being a display processor processing the received continuous output read accessed data to generate display data;

a detector circuit coupled to receive addresses generated by the address generator, the detector circuit generating a detector signal in response to detection of a change in a received address;

a delaying circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the delaying circuit delaying generating of the addresses by the address generator in response to the received detector signal; and

a display monitor coupled to the display processor and displaying an image in response to the display data.

21. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator; and

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address.

35. A memory system as set forth in claim 21, wherein the memory includes a plurality of random access memories storing the data and wherein the memory system further comprises:

an external scanout address update circuit coupled to the plurality of detector circuits and updating the address generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to the plurality of detector circuits and updating the address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

22. A memory system comprising:

a dynamic random access memory storing data to be processed in dynamic form;

an address generator generating an address;

a processor coupled to the dynamic random access memory and coupled to the address generators, the processor processing data stored by the dynamic random access memory in response to the address generated by the address generator;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address; and

a refresh circuit coupled to the memory, coupled to the processor, and refreshing the data stored by the dynamic random access memory in response to the processing of the data by the processor.

23. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator; and

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address, wherein at least one of the plurality of detector circuits includes a comparator circuit generating a comparator detector signal in response to detection of a change in the address generated by the address generator.

24. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address; and

a delaying circuit coupled to receive a detector signal generated by at least one of the plurality of detector circuits, coupled to the address generator, and delaying generating of the address by the address generator in response to the received detector signal.

25. A memory system comprising:

a refreshable memory storing dynamic data;

an address generator generating an address;

a processor coupled to the refreshable memory and coupled to the address generator, the processor processing dynamic data stored by the refreshable memory in response to the address generated by the address generator;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the refresh circuit, coupled to the processor, and generating a refresh control signal in response to the processing of the dynamic data by the processor and in response to the refresh input signal to resolve contention between the processing of the dynamic data by the processor and the refresh input signal; and

a memory refresh circuit refreshing the dynamic data stored by the refreshable memory in response to the refresh control signal.

26. A memory system comprising:

a dynamic random access memory storing dynamic data;

an address generator generating an address having more significant bits and having less significant bits;

an extended read accessing circuit coupled to read access dynamic data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the extended read accessing circuit continually generating output read accessed data extended without interruption during a plurality of read operations by read accessing dynamic data stored by the dynamic random access memory in response to the received address generated by the address generator;

a processor coupled to the dynamic random access memory and to the address generator and processing dynamic data stored by the dynamic random access memory in response to the address generated by the address generator;

a plurality of detector circuits coupled to receive the address generated by the address generator, the plurality of detector circuits generating a plurality of detector signals in response to detection of a change in the received address;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the refresh circuit, coupled to the processor, and generating a refresh control signal in response to the processing of dynamic data by the processor and in response to the refresh input signal to resolve contention between the processing of dynamic data by the processor and the refresh input signal; and

a memory refresh circuit refreshing the data stored by the dynamic random access memory in response to the refresh control signal.

27. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a continuous output extended tristate read accessing circuit coupled to receive the address generated by the address generator and coupled to read access data stored by the dynamic random access memory, the continuous output extended tristate read accessing circuit generating continuously output read accessed data that is extended without tristate interruption during a plurality of read accessing operations; and

a processor coupled to receive the continuously output read accessed data generated by the continuous output extended tristate read accessing circuit, the processor generating processed data in response to the received continuously output read accessed data.

28. A memory system comprising:

a data memory storing data to be processed;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a program memory storing a computer program;

a processor coupled to the data memory and to the address generator and processing data stored by the data memory in response to the address generated by the address generator, the processor being a stored program computer coupled to receive data stored by the data memory and coupled to receive the computer program stored by the program memory, the stored program computer generating processed output data by processing the received data in response to the received computer program;

a write accessing circuit coupled to the data memory, coupled to receive the address generated by the address generator, and coupled to receive the processed output data generated by the stored program computer, the write accessing circuit writing data into the data memory in response to the received address and in response to the received processed output data.

29. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator, the processor being a display processor coupled to receive data stored by the memory, the display processor generating display data by processing the received data; and

a display monitor coupled to receive the display data generated by the display processor, the display monitor displaying an image in response to the received display data.

30. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address; and

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator, the processor being an artificial intelligence processor coupled to receive data stored by the memory, the artificial intelligence processor generating artificial intelligence output data by processing the received data.

31. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator, the processor being an image processor coupled to receive the data stored by the memory, the image processor generating image display data by processing the received data; and

a display monitor coupled to receive image display data generated by the image processor, the display monitor displaying an image in response to the received image display data.

32. A memory system comprising:

a memory storing data to be processed;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a processor coupled to the memory and to the address generator and processing data stored by the memory in response to the address generated by the address generator, the processor being a television image processor coupled to receive data stored by the memory, the television image processor generating television image data by processing the received data; and

a television monitor coupled to receive the television image data generated by the television image processor, the television monitor displaying a television image in response to the received television image data.

33. A memory system comprising:

a data memory storing data to be processed;

an address generator generating an address;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a read only memory storing a computer program; and

a processor coupled to the data memory and to the address generator and processing data stored by the data memory in response to the address generated by the address generator, the processor being a stored program computer coupled to receive data stored by the data memory and coupled to receive the computer program stored by the read only memory, the stored program computer generating processed output data by processing the received data in response to the received program.

34. A memory system comprising:

a plurality of random access memories storing data to be processed;

an address generator generating an address;

a processor coupled to the plurality of random access memories and to the address generator and processing data stored by the plurality of random access memories in response to the address generated by the address generator;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address;

a scanout address update circuit coupled to the plurality of detector circuits and coupled to the address generator, the scanout address update circuit updating the address generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to the plurality of detector circuits and coupled to the address generator, the re-addressing address update circuit updating the address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

36. A memory system comprising:

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address; and

a address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal.

38. A memory system as set forth in claim 36, wherein the detector circuit includes an overflow circuit generating the detector signal in response to detection of an overflow in the address generated by the address generator.

40. A memory system as set forth in claim 36, wherein the detector circuit includes an anticipatory circuit generating the detector signal in response to anticipation of a change in the address generated by the address generator.

43. A memory system as set forth in claim 36, wherein the memory includes:

a refreshable memory circuit storing the data as dynamic data;

a refresh circuit generating a refresh input signal;

a control circuit coupled to the refresh circuit, coupled to the processor, and generating a refresh control signal in response to the processing of data by the processor and in response to the refresh input signal to resolve contention between the processing of the data by the processor and the refresh input signal; and

a memory refresh circuit refreshing the dynamic data stored by the refreshable memory circuit in response to the refresh control signal.

46. A memory system as set forth in claim 36, further comprising a program memory storing a computer program;

wherein the processor includes a stored program computer coupled to the program memory and processing the continuous output data in response to the program stored by the program memory.

47. A memory system as set forth in claim 36, wherein the processor includes a display processor processing the continuous output data to generate display data;

wherein the memory system further comprises a display monitor coupled to the display processor and displaying an image in response to the display data.

48. A memory system as set forth in claim 36, wherein the processor includes an artificial intelligence processor processing the continuous output data to generate artificial intelligence data.

50. A memory system as set forth in claim 36, further comprising a read only memory storing a computer program;

wherein the processor includes a stored program computer coupled to the read only memory and processing the continuous output data in response to the program stored by the read only memory.

53. A memory system as set forth in claim 36, wherein the address update circuit comprises:

an external scanout address update circuit coupled to the detector circuit and updating the address generated by the address generator at a first address update rate in response to a first state of the detector signal and

a re-addressing address update circuit coupled to the detector circuit and updating the address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal.

37. A memory system comprising:

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address;

an address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal; and

a refresh circuit coupled to the dynamic random access memory, coupled to the processor, and refreshing the data stored by the dynamic random access memory in response to the processing of the received continuous output data by the processor.

39. A memory system comprising:

a dynamic random access memory storing data to be processed,

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a comparator detector circuit coupled to receive the address generated by the address generator, the comparator detector circuit generating a detector signal in response to detection of a change in the received address generated by the address generator; and

an address update circuit coupled to receive the detector signal generated by the comparator detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal.

41. A memory system comprising

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a continuous tristate control circuit generating a tristate control signal to continuously enable a continuous tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit executing read access operations to access data stored by the dynamic random access memory in response to the received address;

the continuous tristate memory output circuit coupled to receive data accessed from the memory accessing circuit and coupled to receive the tristate control signal generated by the continuous tristate control circuit, the continuous tristate memory output circuit generating continuous output data without tristate disable during a plurality of read access operations response to the received tristate control signal and in response to the received accessed data;

a processor coupled to the continuous tristate memory output circuit and processing the continuous output data generated be the continuous tristate memory output circuit;

a detector circuit coupled to the address generator and generating a detector signal in response to the address generated by the address generator; and

an address update circuit coupled to the address generator, coupled to the detector circuit, and updating the address generated by the address generator in response to the detector signal generated by the detector circuit.

42. A memory system comprising:

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address;

an address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal; and

a delaying circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the delaying circuit delaying generating of the address by the address generator in response to the received detector signal.

44. A memory system comprising:

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address;

an address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal; and

the dynamic random access memory comprising;

a) a dynamic random access memory circuit storing the data as dynamic data,

b) a refresh circuit generating a refresh input signal,

c) a control circuit coupled to the refresh circuit, coupled to the processor, and generating a refresh control signal in response to the processing of data by the processor and in response to the refresh input signal to resolve contention between the processing of data by the processor and the refresh input signal, and

d) a memory refresh circuit refreshing the dynamic data stored by the dynamic random access memory circuit in response to the refresh control signal.

45. A memory system comprising:

a plurality of dynamic random access memories storing data;

an extended read accessing circuit coupled to read access data stored by the plurality of dynamic random access memories, the extended read accessing circuit read accessing the data stored by the plurality of dynamic random access memories to generate output read accessed data extended without interruption during a plurality of read operations; and

a processor coupled to receive the output read accessed data that is extended without interruption during a plurality of read operations, the processor generating processed output data in response to the received output read accessed data.

49. A memory system comprising:

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address;

an address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal;

an image processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the image processor generating image display data by processing the received continuous output data; and

a display monitor coupled to receive the image display data generated by the image processor, the display monitor displaying an image in response to the received image display data.

51. A memory system comprising:

a dynamic random access memory storing data to be processed, the dynamic random access memory including a cache memory storing the data;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address; and

an address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the address update circuit updating the address generated by the address generator in response to the received detector signal.

52. A memory system comprising:

a dynamic random access memory storing data to be processed;

an address generator generating an address;

a tristate control circuit generating a tristate control signal to continuously enable an extended tristate memory output circuit during a plurality of read access operations;

a memory accessing circuit coupled to access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the memory accessing circuit performing read access operations to access data stored by the dynamic random access memory in response to the received address;

the extended tristate memory output circuit coupled to receive accessed data accessed by the memory accessing circuit and coupled to receive the tristate control Signal generated by the tristate control circuit, the extended tristate memory output circuit generating continuous output data extended without tristate disable during a plurality of sequential read access operations in response to the received tristate control signal and in response to the received accessed data;

a processor coupled to receive the continuous output data generated by the extended-tristate memory output circuit, the processor generating processed output data by processing the received continuous output data;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address;

a scanout address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the scanout address update circuit updating the address generated by the address generator at a first address update rate in response to a first state of the received detector signal; and

a re-addressing address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the re-addressing address update circuit updating the address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the received detector signal.

54. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating addresses, each address having less significant bits and more significant bits;

an extended read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive the addresses generated by the address generator, the extended read accessing circuit generating output read accessed data extended without interruption during a plurality of read operations by read accessing data stored by the dynamic random access memory in response to the addresses generated by the address generator;

a buffer circuit coupled to receive the addresses generated by the address generator, the buffer circuit buffering the more significant bits of an address received from the address generator; and

a comparator circuit coupled to receive the addresses generated by the address generator and coupled to receive the more significant bits of an address buffered by the buffer circuit the comparator generating a detector signal in response to comparison of the received more significant bits of the address and the more significant bits of an address received from the address generator.

55. A memory system comprising:

a memory storing data;

an address generator generating An address having less significant bits and having more significant bits;

an accessing circuit coupled to the memory, coupled to the address generator, and accessing data stored by the memory in response to the address generated by the address generator;

a detector circuit coupled to the address generator and generating a detector signal in response to the more significant bits of the address generated by the address generator;

a buffer circuit coupled to the address generator, coupled to the detector circuit, and buffering the more significant bits of the address in response to the detector signal; and

a comparator circuit coupled to the address generator, coupled to the buffer circuit, and generating a comparator signal in response to comparison of the more significant bits of the address buffered by the buffer circuit and the more significant bits of the address generated by the address generator.

56. A memory system comprising:

a memory storing data;

a first address generator generating a first address;

a second address generator generating a second address;

an accessing circuit coupled to the memory, coupled to the first address generator, coupled to the second address generator, and accessing data stored by the memory in response to the first address generated by the first address generator and in response to the second address generated by the second address generator;

a first detector circuit coupled to the first address generator and generating a first detector signal in response to detection of a change in the first address generated by the first address generator;

a second detector circuit coupled to the second address generator and generating a second detector signal in response to detection of a change in the second address generated by the second address generator; and

a delay circuit coupled to the first detector circuit, coupled to the second detector circuit, coupled to the first address generator, coupled to the second address generator, and delaying generating of the first address by the first address generator in response to the first detector signal and in response to the second detector signal and delaying generating of the second address by the second address generator in response to the first detector signal and in response to the second detector signal.

57. A memory system comprising:

a memory storing data;

a first address generator generating a first address having less significant bits and having more significant bits;

a second address generator generating a second address having less significant bits and having more significant bits;

an accessing circuit coupled to the memory, coupled to the first address generator, coupled to the second address generator, and accessing data stored by the memory in response to the first address generated by the first address generator and in response to the second address generated by the second address generator;

a first detector circuit coupled to the first address generator and generating a first detector signal in response to detection of a change in the more significant bits of the first address generated by the first address generator;

a second detector circuit coupled to the second address generator and generating a second detector signal in response to detection of a change in the more significant bits of the second address generated by the second address generator; and

a delaying circuit coupled to the first detector circuit, coupled to the second detector circuit, coupled to the first address generator, coupled to the second address generator, and delaying generating of the first address by the first address generator in response to the first detector signal and in response to the second detector signal and delaying generating of the second address by the second address generator in response to the first detector signal and in response to the second detector signal.

58. A memory system comprising:

a memory storing data in an X dimension and in a Y dimension array of data;

an X dimension address generator generating an X dimension address having less significant X dimension address bits and having more significant X dimension address bits;

a Y dimension address generator generating a Y dimension address having less significant Y dimension address bits and having more significant Y dimension address bits;

an accessing circuit coupled to the memory, coupled to the X dimension address generator, coupled to the Y dimension address generator, and accessing the X dimension and the Y dimension array of data stored by the memory in response to the X dimension address generated by the X dimension address generator and in response to the Y dimension address generated by the Y dimension address generator;

a processor coupled to the accessing circuit and processing the X dimension and the Y dimension array of data accessed by the accessing circuit;

an X dimension detector circuit coupled to the X dimension address generator and generating an X dimension detector signal in response to detection of a change in the more significant YXdimension address bits of the X dimension address generated by the X dimension address generator;

a Y dimension detector circuit coupled to the Y dimension address generator and generating a Y dimension detector signal in response to detection of a change in the more significant Y dimension address bits of the Y dimension address generated by the Y dimension address generator; and

a delay circuit coupled to the X dimension detector circuit, coupled to the Y dimension detector circuit, coupled to the X dimension address generator, coupled to the Y dimension address generator, and delaying generating of the X dimension address bit the X dimension address generator in response to the X dimension detector signal and in response to the Y dimension detector signal and delaying generating of the Y dimension address by the Y dimension address generator in response to the X dimension detector signal and in response to the Y dimension detector signal.

59. A memory system comprising:

a memory storing data;

a first address generator generating a first address;

a second address generator generating a second address;

an accessing circuit coupled to the memory, coupled to the first address generator, coupled to the second address generator, and accessing data stored by the memory in response to the first address generated by the first address generator and in response to the second address generated by the second address generator;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit;

a first detector circuit coupled to the first address generator and generating a first detector signal in response to detection of a change in the first address generated by the first address generator;

a second detector circuit coupled to the second address generator and generating a second detector signal in response to detection of a change in the second address generated by the second address generator; and

a delay circuit coupled to the first address generator, coupled to the second address generator, coupled to the first detector circuit, and coupled to the second detector circuit, delaying generation of the first address by the first address generator in response to the first detector signal and in response to the second detector signal, and delaying generation of the second address by the second address generator in response to the first detector signal and in response to the second detector signal.

60. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating an address;

an extended tristate read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the extended tristate read accessing circuit read accessing data stored by the dynamic random access memory in response to the received address, the extended tristate read accessing circuit generating output data that is extended during a plurality of read accessing operations without tristate disable in response to the read accessed data and in response to a tristate control signal;

an extended tristate control circuit coupled to the extended tristate read accessing circuit, the extended tristate control circuit generating the tristate control Signal to disable the extended tristate read accessing circuit after generating output data that is extended during the plurality of read accessing operations without tristate disable; and

a detector circuit coupled to the address generator and generating a detector signal in response to the address generated by the address generator.

61. A memory system comprising:

a plurality of random access memories storing data;

an address generator generating an address having less significant bits and having more significant bits;

an accessing circuit coupled to the plurality of random access memories, coupled to the address generator, and accessing data stored by the random access memories in response to the address generated by the address generator;

a detector circuit coupled to the address generator and generating a detector signal in response to detection of a change in the more significant bits of the address generated by the address generator;

a scanout address update circuit coupled to the detector circuit and updating the address generated by the address generator at a first address update rate in response to a first state of the detector signal; and

a re-addressing address update circuit coupled to the detector circuit and updating the address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal.

62. A memory system comprising:

a plurality of dynamic random access memories storing data;

an address generator generating addresses, each address having less significant bits and having more significant bits;

an extended read accessing circuit coupled to read access data stored by the plurality of dynamic random access memories and coupled to receive addresses generated by the address generator, the extended read accessing circuit read accessing data stored by the plurality of dynamic random access memories in response to the received addresses, the extended read accessing circuit generating output read accessed data extended without interruption during a plurality of read operations in response to the read accessed data;

a detector circuit coupled to receive the addresses generated by the address generator, the detector circuit generating a detector signal in response to detection of changes in the more significant bits of the received addresses;

a scanout address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the scanout address update circuit updating the addresses generated by the address generator at a first address update rate in response to a first state of the received detector signal; and

a re-addressing address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the re-addressing address update circuit updating the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the received detector signal.

63. A memory system comprising:

a dynamic random access memory storing data in dynamic form;

an accessing circuit coupled to the dynamic random access memory and accessing data stored by the dynamic random access memory;

a line sync circuit generating a line sync signal;

a dynamic random access memory refresh circuit coupled to the dynamic random access memory, coupled to the line sync circuit, and refreshing data stored by the dynamic random access memory in response to the line sync signal;

a display refresh circuit coupled to the accessing circuit, coupled to the line sync circuit, and generating a display refresh signal in response to data accessed by the accessing circuit and in response to the line sync signal; and

a display device coupled to the display refresh circuit and displaying an image in response to the display refresh signal generated by the display refresh circuit.

64. A memory system comprising:

a memory storing data;

an address generator generating an address having more significant bits and having less significant bits;

a processor coupled to the memory, coupled to the address generator, and processing data stored by the memory in response to the address generated by the address generator;

a configuration circuit coupled to the address generator and generating a plurality of configuration address bits by selecting a plurality of the more significant bits of the address;

a detector circuit coupled to the configuration circuit and generating a detector signal in response to detection of a change in the plurality of configuration address bits generated by the configuration circuit; and

a delaying circuit coupled to the address generator, coupled to the detector circuit, and delaying generating of the address by the address generator in response to the detector signal generated by the detector circuit.

65. A memory system comprising:

a memory storing data;

an address generator generating addresses, each address having less significant bits and having more significant bits;

a buffer circuit coupled to the address generator and buffering the less significant bits and the more significant bits of addresses generated by the address generator;

an accessing circuit coupled to the memory, coupled to the buffer circuit, and accessing data stored by the memory in response to the addresses buffered by the buffer circuit;

a comparator circuit coupled to the address generator, coupled to the buffer circuit, and generating a detector signal in response to comparison of the more significant bits of an address buffered by the buffer circuit and the more significant bits of an address generated by the address generator; and

a delay circuit coupled to the comparator circuit and delaying generating of the addresses by the address generator in response to the detector signal.

66. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating an address;

a continuous output extended tristate read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the continuous output extended tristate read accessing circuit read accessing data stored by the dynamic random access memory in response to the received address, the continuous output extended tristate read accessing circuit generating continuously output data that is extended without tristate interruption during a plurality of read accessing operations;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address.

67. A memory system comprising:

a memory storing data;

a first address generator generating a first address;

a second address generator generating a second address;

a first address initialization number generator generating a first address initialization number;

a second address initialization number generator generating a second address initialization number;

a first address change number generator generating a first address change number;

a second address change number generator generating a second address change number;

a first address initialization circuit coupled to the first address generator, coupled to the first address initialization number generator, and initializing the first address generator in response to the first address initialization number;

a second address initialization circuit coupled to the second address generator, coupled to the second address initialization number generator, and initializing the second address generator in response to the second address initialization number;

a first address update circuit coupled to the first address generator, coupled to the first address change number generator, and updating the first address generator in response to the first address change number;

a second address update circuit coupled to the second address generator, coupled to the second address change number generator, and updating the second address generator in response to the second address change number;

an accessing circuit coupled to the memory, coupled to the first address generator, coupled to the second address generator, and accessing data stored by the memory in response to the first address generated by the first address generator and in response to the second address generated by the second address generator;

a first detector circuit coupled to the first address generator and generating a first detector signal in response to detection of a change in the first address generated by the first address generator; and

a second detector circuit coupled to the second address generator and generating a second detector signal in response to detection of a change in the second address generated by the second address generator.

68. A memory system comprising:

a memory storing data;

a first address generator generating a first address;

a second address generator generating a second address;

a third address generator generating a third address;

a forth address generator generating a forth address;

a first address change number generator generating a first address change number;

a second address change number generator generating a second address change number;

a third address change number generator generating a third address change number;

a forth address change number generator generating a forth address change number;

a first address initialization circuit coupled to the first address generator, coupled to the third address generator, and initializing the first address generator in response to the third address;

a second address initialization circuit coupled to the second address generator, coupled to the forth address generator, and initializing the second address generator in response to the forth address;

a first address Update circuit coupled to the first address generator, coupled to the first address change number generator, and updating the first address generator in response to the first address change number;

a second address update circuit coupled to the second address generator, coupled to the second address change number generator, and updating the second address generator in response to the second address change number;

a third address update circuit coupled to the third address generator, coupled to the third address change number generator, and updating the third address generator in response to the third address change number;

a forth address update circuit coupled to the forth address generator, coupled to the forth address change number generator, and updating the forth address generator in response to the forth address change number; and

an accessing circuit coupled to the memory, coupled to the first address generator, coupled to the second address generator, and accessing data stored by the memory in response to the first address generated by the first address generator and in response to the second address generated by the second address generator.

69. A memory system comprising:

a plurality of dynamic random access memories storing data

an address generator generating an address;

a continuous output tristate read accessing circuit coupled to access data stored by the plurality of dynamic random access memories, coupled to receive the address generated by the address generator, and coupled to receive a tristate control signal generated by a tristate control circuit, the continuous output tristate read accessing circuit read accessing data stored by the plurality of dynamic random access memories in response to the received address, the continuous output tristate read accessing circuit generating continuously output data without tristate disable during a plurality of sequential read accessing operations of the plurality of dynamic random access memories in response to the received tristate control signal;

a tristate control circuit coupled to the tristate read accessing circuit, the tristate control circuit generating the tristate control signal to disable the tristate read accessing circuit after generating continuously output data without tristate disable during the plurality of sequential read accessing operations of the plurality of dynamic random access memories;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address.

70. A memory system comprising:

a memory storing data;

an address generator generating an address having more significant bits, having less significant bits, and having least significant bits;

an accessing circuit coupled to the memory, coupled to the address generator, and accessing data stored by the memory in response to the address generated by the address generator;

a first detector circuit coupled to the address generator and generating a first detector signal in response to detection of a change in the more significant bits of the address generated by the address generator;

a second detector circuit coupled to the address generator and generating a second detector signal in response to detection of a change in the less significant bits of the address generated by the address generator;

a first delay circuit coupled to the first detector circuit and delaying generating of the address by the address generator for a first delay in response to the first detector signal; and

a second delay circuit coupled to the second detector circuit and delaying generating of the address by the address generator for a second delay that is different from the first delay in response to the second detector signal.

71. A memory system comprising:

a plurality of dynamic random access memories storing data;

an address generator generating an address;

an extended output tristate read accessing circuit coupled to read access data stored by the plurality of dynamic random access memories, coupled to receive the address generated by the address generator and coupled to receive a tristate control signal, the extended output tristate read accessing circuit read accessing data stored by the plurality of dynamic random access memories in response to the received address, the extended output tristate read accessing circuit generating continuously output data extended during a plurality of sequential read accessing operations without tristate disable of the extended tristate read accessing circuit in response to the read accessed data and in response to the tristate control signal;

a tristate control circuit coupled to the extended output tristate read accessing circuit, the tristate control circuit generating the tristate control signal to disable the extended output tristate read accessing circuit after generating the continuously output data that is extended during the plurality of sequential read accessing operations without tristate disable of the extended tristate read accessing circuit;

a detector circuit coupled to receive the address generated by the address generator, the detector circuit generating a detector signal in response to the received address;

a scanout address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the scanout address update circuit updating the address generated by the address generator at a first address update rate in response to a first state of the received detector signal; and

a re-addressing address update circuit coupled to receive the detector signal generated by the detector circuit and coupled to the address generator, the re-addressing address update circuit updating the address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the received detector signal.

72. A memory system comprising:

a memory storing data and being addressed by row address signal lines, by column address signal lines, and by external scanout address signal lines;

an address generator generating an address having more significant bits coupled to the row address signal lines of the memory, having less significant bits coupled to the column address signal lines of the memory, and having least significant bits coupled to the external scanout address signal lines of the memory;

an accessing circuit coupled to the memory, coupled to the address generator, and accessing data stored by the memory in response to the address generated by the address generator;

a first detector circuit coupled to the address generator and generating a first detector signal in response to detection of a change in the more significant bits of the address generated by the address generator;

a second detector circuit coupled to the address generator and generating a second detector signal in response to detection of a change in the less significant bits of the address generated by the address generator;

a first delay circuit coupled to the first detector circuit, coupled to the address generator, and delaying generating of the address by the address generator by a first delay in response to the first detector signal; and

a second delay circuit coupled to the second detector circuit, coupled to the address generator, and delaying generating of the address by the address generator by a second delay that is shorter than from the first delay in response to the second detector signal.

73. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating an address having more significant bits and having less significant bits;

an extended read accessing circuit coupled to read access data stored by the dynamic random access memory and coupled to receive the address generated by the address generator, the extended read accessing circuit continually generating output read accessed data extended without interruption during a plurality of read operations by read accessing data stored by the dynamic random access memory in response to the received address generated by the address generator; and

a detector circuit coupled to receive the more significant bits of the address generated by the address generator, the detector circuit generating a detector signal in response to detection of a change in the received more significant bits of the address.

74. A memory system comprising:

a memory storing data and being addressed by row address signals on row address signal lines, by column address signals on column address signal lines, and by external scanout address signals an external scanout address signal lines;

a first address generator generating a first address and a second address generator generating a second address, wherein the first address and the second address are coupled to the row address signal lines of the memory to provide the row address signals, wherein the first address and the second address are coupled to the column address signal lines of the memory to provide column address signals, and wherein the first address and the second address are coupled to the external scanout address signal lines of the memory;

an accessing circuit coupled to the memory, coupled to the first address generator, coupled to the second address generator, and accessing data stored by the memory in response to the first address and in response to the second address;

a first detector circuit coupled to the address generator and generating a first detector signal in response to detection of a change in the row address signals on the row address signal lines of the memory;

a second detector circuit coupled to the address generator and generating a second detector signal in response to detection of a change in the column address signals on the column address signal lines of the memory;

a first delay circuit coupled to the first detector circuit, coupled to the first address generator, coupled to the second address generator, and delaying generating of the first address by the first address generator and delaying generation of the second address by the second address generator for a RAS period in response to the first detector signal; and

a second delay circuit coupled to the second detector circuit, coupled to the first address generator, coupled to the second address generator, and delaying generating of the first address by the first address generator and generation of the second address by the second address generator for a CAS period that is shorter than the RAS delay in response to the second detector signal.

75. A memory system comprising:

a dynamic random access memory storing data;

an extended read accessing circuit coupled to read access data stored by the dynamic random access memory, the extended read accessing circuit read accessing the data stored by the dynamic random access memory to generate memory output data extended during a plurality of read operations; and

a processor coupled to receive the memory output data that is extended during a plurality of read operations, the processor generating processed output data in response to the received output read accessed data.

76. A memory system comprising:

a memory storing data;

an address generator generating an address;

a television image processor coupled to the memory, coupled to the address generator, and processing data stored by the memory in response to the address generated by the address generator to generate television image data;

a detector circuit coupled to the address generator and generating a detector signal in response to the address;

a delaying circuit coupled to the detector circuit, coupled to the address generator, and delaying generating of the address by the address generator in response to the detector signal; and

a television monitor coupled to the television image processor and displaying a television image in response to the television image data.