Semiconductor disk system having a plurality of flash memories

• US 5,603,001 A
• Filed: 05/05/1995
• Issued: 02/11/1997
• Est. Priority Date: 05/09/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maki, Yasunori, Sukegawa, Hiroshi, Inagaki, Takashi
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Etienne, Ario
• Application Number:
  US08/435,854
• Time in Patent Office: 648 Days
• Field of Search: 395/404, 395/405, 395/430, 395/185.01, 395/185.05, 395/839, 395/428, 395/441, 395/429, 395/182.04, 395/413, 395/439, 395/440, 395/483, 395/427
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system

Abstract

A NAND bus interface independently receives 16 ready/busy signals from 16 flash EEPROM chips and thereby separately manages the operating states of these flash EEPROMs. Once a flash EEPROM as a write access target is set in a ready state, a write access to this write access target flash EEPROM is started without waiting for completion of the operations of all the flash EEPROMs. Each flash EEPROM is of a command control type capable of automatically executing a write operation. This allows parallel processing of the flash EEPROMs, i.e., a write access to a given EEPROM can be performed while a data write to another flash EEPROM is being executed. An ECC calculating circuit calculates a data string transferred in units of 256 bytes from a data buffer by a processor, and generates an ECC corresponding to that data string. The 256-byte data string is added with the generated ECC and transferred to a data register of a flash EEPROM. Even if abnormal cells are produced at the same bit position in a plurality of pages of a flash EEPROM, only one abnormal cell is contained in a data string as an object of the ECC calculation. This makes it possible to perform error detection and correction by a common simple ECC calculation without using any complicated ECC arithmetic expression with a high data recovery capability.

Claims

1. A semiconductor disk system comprising:

a plurality of flash memories each having a memory cell array constituted by a plurality of blocks, each consisting of a plurality of pages, each of said flash memories automatically executing page write processing for writing data of one of said pages into said memory cell array in response to a write command and generating a ready/busy signal indicating a busy state during the page write processing;

a memory for storing write data transferred from a host system;

setting means for setting, on the basis of the write data, block data to be written into individual said blocks of said flash memories designated by a write access request from said host system, said setting means including;

determining means for determining, for each said designated block, whether a write area requested to perform a data write access is smaller than an overall data write area in said designated block, and

block data setting means for setting the block data by using data to be stored in a non-write area of said designed block and the write data, if said determining means determines that the write area is smaller than the overall data write area,

data transfer means for transferring one said page of the block data set by said setting means to said flash memories designated by the write access request and issuing a write command;

detecting means for detecting completion of the page write access of each of said flash memories to which the data is transferred by said data transfer means, in accordance with the ready/busy signals generated from said flash memories; and

control means for controlling said data transfer means in accordance with the page write access completion detected by said detecting means, such that the set block data is entirely transferred.

2. A semiconductor disk system comprising:

a plurality of flash memories each having a memory cell array constituted by a plurality of blocks, each consisting of a plurality of pages, each of said flash memories automatically executing page write processing for writing data of one of said pages into said memory cell array in response to a write command and generating a ready/busy signal indicating a busy state during the page write processing;

a memory for storing write data transferred from a host system;

setting means for setting, on the basis of the write data, block data to be written into individual said blocks of said flash memories designated by a write access request from said host system;

data transfer means for transferring one said page of the block data set by said setting means to said flash memories blocks designated by the write access request and issuing a write command, said data transfer means includes a predetermined number of channel means for transferring the set block data to said flash memories, and executes data transfer by allocating a predetermined number of flash memories of said designated flash memories blocks to said channel means;

detecting means for detecting completion of the page write access of each of said flash memories to which the data is transferred by said data transfer means, in accordance with the ready/busy signals generated from said flash memories; and

control means for controlling said data transfer means in accordance with the page write access completion detected by said detecting means, such that the set block data is entirely transferred, said control means controls said data transfer means in response to completion of the transfer of given block data, such that a flash memory to which the block data has not been transferred is allocated to channel means to which a flash memory which has completed the transfer of the block data is allocated.

3. A system according to claim 2, further comprising:

second setting means for, if said block designated by a first write access from said host system equals said block designated by a previously issued second write access request and if data transfer to said block designated by the second write access request has not been completed, setting new block data on the basis of write data corresponding to the first write access request and block data set by said setting means in response to the second write access request.

4. A semiconductor disk system comprising:

a flash memory having a memory cell array consisting of a plurality of pages each including a data storage area and a redundancy area, and a data register for holding data of said one said page, data transfer between said data register and said memory cell array being executed in units of pages;

a data buffer for storing write data transferred from a host system and read data read out from said flash memory;

error correction code generating means for performing, in response to a write request from said host system, a calculation for the write data stored in said data buffer in units of data strings each said corresponding to a size of the data storage area of each said page, thereby generating an error correction code for each data string; and

write access means for adding a corresponding error correction code to each data string, in order that each data string and an error correction code corresponding to the data string are written into the data storage area and the redundancy area, respectively, of the same said page, and transferring the data string and the error correction code to said data register, thereby performing a write access to said flash memory.

5. A system according to claim 4, further comprising:

error correction code calculating means for performing a read access to said flash memory in response to a read request from said host system, calculating an error correction code for each said page to be read out, and executing error detection and correction for each data string of each said page.

6. A system according to claim 4, further comprising:

writing means for writing bad sector information indicating a bad sector designated by said host system into the redundancy area of one of said pages of said flash memory which corresponds to the bad sector.

7. A system according to claim 4, further comprising:

writing means for writing error information indicating an ECC error sector designated by said host system into the redundancy area of one of said pages of said flash memory which corresponds to the error sector.

8. A system according to claim 4, further comprising:

a ROM which stores a program to be executed by said host system and to which the program is transferred in response to a read request for a predetermined address from said host system.

9. A system according to claim 4, wherein said flash memory is constituted by an EEPROM (Electrically Erasable and Programmable Read-Only Memory).

10. A semiconductor disk system comprising:

a flash memory having a memory cell array consisting of a plurality of pages each including a data storage area and a redundancy area, and a data register for holding data of one said page, data transfer between said data register and said memory cell array being executed in units of said pages;

a microprocessor;

a data buffer for storing write data transferred from a host system and read data read out from said flash memory;

a flash memory interface circuit, controlled by said microprocessor, for performing a read/write access to said flash memory; and

an I/O registers set capable of being read/written by said microprocessor,

wherein said flash memory interface circuit includes

an error correction code generation circuit for performing a calculation for write data which is read out by said microprocessor from said data buffer in units of data strings each corresponding to a size of the data storage area of each said page, thereby generating an error correction code for each data string,

a write data transfer circuit for adding a corresponding error correction code to each data string, in order that each data string and an error correction code corresponding to the data string are written into the data storage area and the redundancy area, respectively, of the same said page, and transferring the data string and the error correction code to said data register of said flash memory,

a read data transfer circuit for extracting the data string stored in the data storage area from the read data read out from said data register of said flash memory, and transferring the extracted data string to said data buffer,

an error correction code check circuit for executing error detection for the read data by using the error correction code contained in the read data, and setting the detection result in said I/O register, and

said microprocessor is so programmed as to execute error correction for the read data transferred to said data buffer in accordance with the calculation result set in said I/O register.

11. A system according to claim 10, wherein said flash memory is an EEPROM flash memory.

12. A semiconductor disk system comprising:

a flash memory having a memory cell array which includes a plurality of blocks, each said block consisting of a plurality of pages, each said page including a data storage area and a redundancy area, and in which write count information indicative of a write count of each said block is stored in the redundancy area of a predetermined said page of each said block, and a data register for holding data of one said page, data transfer between said data register and said memory cell array being executed in units of said pages, and an erase operation being executed in units of said blocks;

a data buffer for storing write data transferred from a host system and read data read out from said flash memory;

updating means for reading out the write count information from said predetermined page of a write target block which is designated by a write request from said host system, and updating a value of the write count information; and

write access means for generating page data by adding the updated write count information to write data to be written into said predetermined page, and transferring the page data to said data register of said flash memory such that the write data and the updated write count information are stored in the data storage area and the redundancy area, respectively, of said predetermined page, thereby performing a write access to said flash memory.

13. A system according to claim 12, wherein said flash memory is an EEPROM flash memory.

14. A semiconductor disk system comprising:

a flash memory having a memory cell array which includes a plurality of blocks, each said block consisting of a plurality of pages, each said page including a data storage area and a redundancy area, and in which write count data constituted by an upper bit portion of write count data indicative of a write count of each said block is stored in a predetermined said block, and second write count data constituted by a lower bit portion of write count data corresponding to each said block is stored in the redundancy area of a predetermined said page of each said block, and a data register for holding data of one said page, said flash memory being set, in response to a command, in one of an erase operation mode by which stored contents are erased in units of said blocks, a write operation mode by which data is written in said memory cell array in units of said pages, and a read operation mode by which data is read out from said memory cell array in units of said pages;

a data buffer for storing write data transferred from a host system and read data read out from said flash memory;

write count managing means for setting said flash memory in the read operation mode by issuing a read command, reading out the first write count data from said predetermined block, and managing the write count of each said block of said flash memory in accordance with the readout first write count data;

updating means for setting said flash memory in the read operation mode by issuing a read command, reading out the second write count data from said predetermined page of a write target block designated by a write request, and updating a value of the readout second write count data;

header table generating means for reading out data stored in a target page other than a write access target page of said write target block into said data buffer, and, on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer, generating a header table which holds address information indicating a storage position, in said data buffer, of each data constituting block data of one said block to be written into said write target block;

erasing means for setting said flash memory in the erase operation mode by issuing an erase command, and erasing stored contents of said write target block; and

write access means for reading out the block data in said units of said pages from said data buffer by referring to the address information of said header table, and transferring the readout data to said data register, thereby performing a write access to said flash memory,

wherein said write count managing means includes updating means for updating a value of the first write count data corresponding to said write target block, if a carry occurs from the second write count data to the first write count data upon updating the second write count data.

15. A system according to claim 14, wherein said write count managing means includes

determining means for, if the value of the first write count data of said write target block is updated, determining that said block whose write count has a difference reaching a predetermined value from the write count of said write target block is to be used as a swapping destination block, and

swapping means for swapping block addresses and stored contents of said write target block and said swapping destination block.

16. A system according to claim 14, wherein as an initial value of the second write count data, a discrete value is stored beforehand in the redundancy area of said predetermined page of each said block.

17. A system according to claim 14, wherein

said predetermined block stores a swapping table which holds minimum write count information indicating a minimum value of the first write count data of said plurality of blocks and priority information indicating a priority order of plural said swapping destination blocks in accordance with the value of the first write count data, and

said write count managing means includes

determining means for, if the value of the first write count data of said write target block is updated, comparing the write count of said write target block with the value of the minimum write count information in said swapping table, and determining whether a difference between the write counts reaches a predetermined value, and

swapping means for, if the difference between the write counts reaches the predetermined value, determining a swapping destination block with a highest priority by referring to the priority information in said swapping table, and swapping block addresses and stored contents of said write target block and said swapping destination block with the highest priority.

18. A system according to claim 14, wherein said flash memory is an EEPROM flash memory.

19. A semiconductor disk system comprising:

a flash memory having a memory cell array which includes a plurality of blocks, each said block consisting of a plurality of pages, each said page including a data storage area and a redundancy area, and in which write count information indicating a write count of each said block is stored in the redundancy area of a predetermined one of said pages of each said block, and a data register for holding data of one said page, said flash memory being set, in response to an external command, in one of an erase operation mode by which stored contents are erased in units of said blocks, a write operation mode by which data is written in units of said pages in said memory cell array, and a read operation mode by which data is read out in units of said pages from said memory cell array;

a data buffer for holding write data transferred from a host system and read data read out from said flash memory;

updating means for setting said flash memory in the read operation mode by issuing a read command, reading out the write count information from said predetermined page of a write target block designated by a write request, and updating a value of the readout write count information;

header table generating means for, if a target page other than a write access target page exists in said write target block, reading out data stored in said target page other than said write access target page into said data buffer, and, on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer, generating a header table which holds address information indicating a storage position, in said data buffer, of each data constituting block data of one of said blocks to be written into said write target block;

erasing means for setting said flash memory in the erase operation mode by issuing an erase command, and erasing stored contents of said write target block;

first access means for reading out write data to be written into said predetermined page from said data buffer by referring to the address information in said header table, generating page data by adding the updated write count information to the readout write data, and transferring the page data to said data register such that the write data and the updated write count information are stored in the data storage area and the redundancy area, respectively, of said predetermined page, thereby performing a write access to said flash memory; and

second access means for sequentially reading out write data to be written into said pages other than said predetermined page from said data buffer by referring to the address information in said header table, and transferring the read out write data to said data register, thereby performing a write access to said flash memory.

20. A system according to claim 19, further comprising:

reading means for sequentially reading out the block data in units of data strings each corresponding to a size of the data storage area from said data buffer by referring to the address information in said header table; and

error correction code generating means for generating an error correction code for each data string read out from said data buffer, and

wherein said first access means generates page data by adding, to a data string to be written into said predetermined page, an error correction code corresponding to the data string and the updated write count information, and transfers the generated page data to said data register such that the data string is stored in the data storage area of said predetermined page and the updated write count information and the error correction code are stored in the redundancy area of said predetermined page, thereby performing a write access to said flash memory, and

said second access means generates page data by adding a corresponding error correction code to a data string to be written into each page other than said predetermined page, and transfers the generated page data to said data register such that the data string and the error correction code are stored in the data storage area and the redundancy area, respectively, of the corresponding page, thereby performing a write access to said flash memory.

21. A system according to claim 20, wherein said flash memory is an EEPROM flash memory.

22. An access control method in a semiconductor disk system which comprises a plurality of flash memories each having a memory cell array constituted by a plurality of blocks, each said block consisting of a plurality of a plurality of pages, each of said flash memories automatically executing page write processing for writing data of one of said pages into said memory cell array in response to a write command and generating a ready/busy signal indicating a busy state during the page write processing, and a memory for storing write data transferred from a host system, comprising the steps of:

a) setting, on the basis of the write data, block data to be written into individual said blocks of said flash memories designated by a write access request from said host system, said setting step including the substeps of;

determining, for each said designated block, whether a write area requested to perform a data write access is smaller than an overall data write area in each said designated block, and

setting the block data by using data to be stored in a non-write area of each said designated block and the write data, if the determination substep determines that the write area is smaller than the overall data write area;

b) transferring one page of the block data set in the step a) to said flash memories designated by the write access request and issuing a write command;

c) detecting completion of the page write access of each of said flash memories to which the data is transferred in the step b), in accordance with the ready/busy signals generated from said flash memories; and

d) controlling the step b) in accordance with the page write access completion detected in the step c), such that the set block data is entirely transferred.

23. An access control method in a semiconductor disk system which comprises a plurality of flash memories each having a memory cell array constituted by a plurality of blocks, each said block consisting of a plurality of a plurality of pages, each of said flash memories automatically executing page write processing for writing data of one of said pages into said memory cell array in response to a write command and generating a ready/busy signal indicating a busy state during the page write processing, and a memory for storing write data transferred from a host system, comprising the steps of:

a) setting, on the basis of the write data, block data to be written into individual said blocks of said flash memories designated by a write access request from said host system, said semiconductor disk system including a predetermined number of channel means for transferring the set block data to said flash memories;

b) transferring one page of the block data set in the step a) to said flash memories designated by the write access request by allocating a predetermined number of flash memories of said designated flash memories to said channel means, and issuing a write command;

c) detecting completion of the page write access of each of said flash memories to which the data is transferred in the step b), in accordance with the ready/busy signals generated from said flash memories; and

d) controlling the step b) in accordance with the page write access completion detected in the step c), such that the set block data is entirely transferred, said controlling step acting in response to completion of the transfer of given block data, such that a flash memory to which the block data has not been transferred is allocated to channel means to which a flash memory which has completed the transfer of the block data is allocated.

24. A method according to claim 23, further comprising the step of:

if one of said blocks designated by a first write access from said host system equals another of said blocks designated by a previously issued second write access request and if data transfer to said another block designated by the second write access request has not been completed, setting new block data on the basis of write data corresponding to the first write access request and block data set by the setting substep in response to the second write access request.

25. A data hold control method in a semiconductor disk system which comprises a flash memory having a memory cell array consisting of a plurality of pages, each including a data storage area and a redundancy area, and a data register for holding data of one page, data transfer between said data register and said memory cell array being executed in units of said pages, and a data buffer for storing write data transferred from a host system and read data read out from said flash memory, comprising the steps of:

a) in response to a write request from said host system, performing a calculation for the write data stored in said data buffer in units of data strings, each corresponding to a size of the data storage data of each said page, thereby generating an error correction code for each data string; and

b) adding a corresponding error correction code to each said data string, in order that each said data string and an error correction code corresponding to each said data string are written into the data storage area and the redundancy area, respectively, of a corresponding one of said pages, and transferring the data string and the error correction code of the corresponding said page to said data register, thereby performing a write access to said flash memory.

26. A method according to claim 25, further comprising the step of:

performing a read access to said flash memory in response to a read request from said host system, calculating an error correction code for each said page to be read out, and executing error detection and correction for each said data string of each said page.

27. A method according to claim 25, further comprising the step of:

writing bad sector information indicating a bad sector designated by said host system into the redundancy area of one of said pages of said flash memory which corresponds to the bad sector.

28. A method according to claim 25, further comprising the step of:

writing error information indicating an ECC error sector designated by-said host system into the redundancy area of one of said pages of said flash memory which corresponds to the error sector.

29. An access control method in a semiconductor disk system which comprises a flash memory having a memory cell array which includes a plurality of blocks, each said block consisting of a plurality of pages, each said page including a data storage area and a redundancy area, and in which write count information indicative of a write count of each said block is stored in the redundancy area of a predetermined one of said pages of one of said blocks, and a data register for holding data of one of said pages, data transfer between said data register and said memory cell array being executed in units of said pages, and an erase operation being executed in units of said blocks, and a data buffer for storing write data transferred from a host system and read data read out from said flash memory, comprising the steps of:

a) reading out the write count information from a predetermined page of a write target block which is designated by a write request from said host system, and updating a value of the write count information;

b) generating page data by adding the updated write count information to write data to be written into said predetermined page; and

c) transferring the page data to said data register of said flash memory such that the write data and the updated write count information are stored in the data storage area and the redundancy area, respectively, of said predetermined page, thereby performing a write access to said flash memory.

30. An access control method in a semiconductor disk system which comprises a flash memory having a memory cell array which includes a plurality of blocks, each said block consisting of a plurality of pages, each said page including a data storage area and a redundancy area, and in which first write count data constituted by an upper bit portion of write count data indicative of a write count of each said block is stored in a predetermined one of said blocks, and second write count data constituted by a lower bit portion of write count data corresponding to each said block is stored in the redundancy area of a predetermined page of said predetermined block, and a data register for holding data of one said page, said flash memory being set, in response to a command, in one of an erase operation mode by which stored contents are erased in units of said blocks, a write operation mode by which data is written in said memory cell array in units of said pages, and a read operation mode by which data is read out from said memory cell array in units of said pages, and a data buffer for storing write data transferred from a host system and read data read out from said flash memory, comprising the steps of:

a) setting said flash memory in read operation mode by issuing a read command, reading out the first write count data from said predetermined block, and managing the write count of each said block of said flash memory in accordance with the readout first write count data;

b) setting said flash memory in the read operation mode by issuing a read command, reading out the second write count data from a predetermined page of a write target block designated by a write request, and updating a value of the readout second write count data;

c) reading out data stored in a target page other than a write access target page of said write target block into said data buffer, and, on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer, generating a header table which holds address information indicating a storage position, in said data buffer, of each data constituting block data of one of said blocks to be written into said write target block;

d) setting said flash memory in the erase operation mode by issuing an erase command, and erasing stored contents of said write target block; and

e) reading out the block data in units of said pages from said data buffer by referring to the address information of said header table, and transferring the read out data to said data register, thereby performing a write access to said flash memory,

wherein the step a) includes the step of updating a value of the first write count data corresponding to said write target block, if a carry occurs from the second write count data to the first write count data upon updating the second write count data.

31. A method according to claim 30, wherein the step a) includes the steps of

if the value of the first write count data of said write target block is updated, determining that one said block whose write count has a difference reaching a predetermined value from the write count of said write target block is to be used as a swapping destination block, and

swapping block addresses and stored contents of said write target block and said swapping destination block.

32. A method according to claim 31, further comprising the step of:

storing a discrete value beforehand in the redundancy area of said predetermined page of each said block, as an initial value of the second write count data.

33. A method according to claim 30, wherein

said predetermined block stores a swapping table which holds minimum write count information indicating a minimum value of the first write count data of said plurality of blocks and priority information indicating a priority order of swapping destination blocks in accordance with the value of the first write count data, and

the step a) includes the steps of

if the value of the first write count data of said write target block is updated, comparing the write count of said write target block with the value of the minimum write count information in said swapping table, and determining whether a difference between the write counts reaches a predetermined value, and

if the difference between the write counts reaches a predetermined value, determining a swapping destination block with a highest priority by referring to the priority information in said swapping table, and swapping block addresses and stored contents of said write target block and said swapping destination block with the highest priority.

34. An access control method in a semiconductor disk system which comprises a flash memory having a memory cell array which includes a plurality of blocks, each said block consisting of a plurality of pages, each said page including a data storage area and a redundancy area, and in which write count information indicating a write count of each said block is stored in the redundancy area of a predetermined page of each said block, and a data register for holding data of one said page, said flash memory being set, in response to an external command, in one of an erase operation mode by which stored contents are erased in units of said blocks, a write operation mode by which data is written in units of said pages in said memory cell array, and a read operation mode by which data is read out in units of said pages from said memory cell array, and a data buffer for holding write data transferred from a host system and read data read out from said flash memory, comprising the steps of:

a) setting said flash memory in the read operation mode by issuing a read command, reading out the write count information from a predetermined page of a write target block designated by a write request, and updating a value of the read out write count information;

b) if a target page other than a write access target page exists in said write target block, reading out data stored in said target page other than said write access target page into said data buffer, and, on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer, generating a header table which holds address information indicating a storage position, in said data buffer, of each data constituting block data of one of said blocks to be written into said write target block;

c) setting said flash memory in the erase operation mode by issuing an erase command, and erasing stored contents of said write target block;

d) reading out write data to be written into said predetermined page from said data buffer by referring to the address information in said header table, generating page data by adding the updated write count information to the readout write data, and transferring the page data to said data register such that the write data and the updated write count information are stored in the data storage area and the redundancy area, respectively, of said predetermined page, thereby performing a write access to said flash memory; and

e) sequentially reading out write data to be written into said pages other than said predetermined page from said data buffer by referring to the address information in said header table, and transferring the read out write data to said data register, thereby performing a write access to said flash memory.

35. A method according to claim 34, further comprising the steps of:

f) sequentially reading out the block data in units of data strings each corresponding to a size of the data storage area from said data buffer by referring to the address information in said header table; and

g) generating an error correction code for each data string read out from said data buffer, and

wherein the step d) generates page data by adding, to a data string to be written into said predetermined page, an error correction code corresponding to the data string and the updated write count information, and transfers the generated page data to said data register such that the data string is stored in the data storage area of said predetermined page and the updated write count information and the error correction code are stored in the redundancy area of said predetermined page, thereby performing a write access to said flash memory, and

the step e) generates page data by adding a corresponding error correction code to a data string to be written into each said page other than said predetermined page, and transfers the generated page data to said data register such that the data string and the error correction code are stored in the data storage area and the redundancy area, respectively, of the corresponding page, thereby performing a write access to said flash memory.