Power management system for components used in battery powered applications
First Claim
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1. A control circuit for a computer component circuit, the control circuit comprising:
- a microprocessor;
a series of gates controlled by the microprocessor;
an oscillator for providing square wave pulses at a prescribed frequency;
a clock signal generation circuit coupled to the oscillator and the gates for generating clock pulses from the square wave pulses for use by the computer component circuit;
a first process run by the microprocessor to control the gates to disable the oscillator and the clock signal generation circuit at the completion of any operation by the component circuit such that the clock pulses are disabled before the square wave pulses are disabled; and
a second process run by the microprocessor to control the gates to enable the oscillator and the clock signal generation circuit in response to any command to the component circuit from a host computer.
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Abstract
A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.
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Citations
10 Claims
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1. A control circuit for a computer component circuit, the control circuit comprising:
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a microprocessor; a series of gates controlled by the microprocessor; an oscillator for providing square wave pulses at a prescribed frequency; a clock signal generation circuit coupled to the oscillator and the gates for generating clock pulses from the square wave pulses for use by the computer component circuit; a first process run by the microprocessor to control the gates to disable the oscillator and the clock signal generation circuit at the completion of any operation by the component circuit such that the clock pulses are disabled before the square wave pulses are disabled; and a second process run by the microprocessor to control the gates to enable the oscillator and the clock signal generation circuit in response to any command to the component circuit from a host computer. - View Dependent Claims (2)
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3. A computer subsystem joined to a computer system having a central processing unit and a bus, the subsystem comprising:
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a microprocessor for managing the subsystem; an oscillator for generating a repeating pattern of signals; a clock generator for providing clock signals from the repeating pattern of signals; and a series of gates for controlling the transfer of signals from and to the oscillator to selectively disable the oscillator and the clock generator from generating the clock signals and the repeating pattern of signals in response to commands from the microprocessor such that the clock signals are disabled before the repeating pattern of signals is disabled. - View Dependent Claims (4, 5)
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6. A computer system, comprising:
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a central processing unit; a main memory; a bus for transferring signals within the computer system; and a subsystem joined to the bus, the subsystem comprising a control circuit that includes a microprocessor for managing the subsystem, an oscillator for generating a repeating pattern of signals, a clock generator for providing clock signals from the repeating pattern of signals, and a series of gates for controlling the transfer of signals from and to the oscillator to selectively disable the oscillator and the clock generator from generating the clock signals and the repeating pattern of signals in response to the completion of any operation by the subsystem. - View Dependent Claims (7, 8, 9)
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10. A method for controlling the use of power in a computer subsystem including a microprocessor for managing the subsystem, an oscillator for generating a repeating pattern of signals, and a clock generator for providing clock signals from the repeating pattern of signals, comprising the steps of:
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selectively disabling the generation of the clock signals and the repeating pattern of signals in response to commands from the microprocessor after the termination of any operation by a host computer which utilizes the computer subsystem such that the clock signals are first disabled before the repeating pattern of signals is disabled, and enabling the generation of the clock signals and the repeating pattern of signals in response to any command to the computer subsystem from a host computer system such that the clock signals are not enabled until the repeating pattern of signals has established a full wave pattern.
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Specification