System for compiling algorithmic language source code for implementation in programmable hardware

• US 5,603,043 A
• Filed: 04/03/1995
• Issued: 02/11/1997
• Est. Priority Date: 11/05/1992
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Giga Operations Corporation
• Inventors: Dowling, Robert, Taylor, Brad
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/415,750
• Time in Patent Office: 680 Days
• Field of Search: 395/800
• US Class Current: 712/1
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A configurable hardware system for implementing an algorithmic language program, including at least two programmable logic devices (PLD), a private hardware resource connectible to one PLD, and a programmable connection between PLDs, all of which may be configured as a module or distributed processing units (DPU). The private hardware resource may include a serial processing device such as a DSP, a PLD, a memory device, or a CPU. An extensible processing unit (EPU) can be built out of multiple DPUs, each connected to other modules by one or more of several buses. An N-bus (neighbor bus) connects a module to its nearest neighbor, an M-bus (module bus) connects a group of modules, and an H-bus (host bus) connects a module to a host CPU. The invention also includes a method of translating source code in an algorithmic language into a configuration file for implementation on one or more DPUs. The method includes four sequential phases of translation, a tokenizing phase, a logical mapping phase, a logic optimization phase, and a device specific mapping phase.

Claims

1. A configurable hardware module comprising:

a first and a second programmable logic device (PLD), each said PLD comprising a plurality of programmable pins for connection to one or more devices and also comprising internal programmable interconnect and configurable logic, at least one of said programmable pins connectible through said programmable interconnect to said configurable logic;

a configurable bus directly connecting said first PLD and said second PLD, said configurable bus comprising a plurality of configurable bus lines, each of said configurable bus lines comprising a connection between a programmable pin on said first PLD and a corresponding programmable pin on said second PLD;

a private hardware resource directly connectible to said second PLD but not to said first PLD; and

a means for configuring said first PLD and said second PLD,

whereby at least one of said configurable bus lines can be connected at a first time for communication between first configurable logic in said first PLD and first configurable logic in said second PLD to communicate a first signal and

connected at a second time for communication between second configurable logic in said first PLD and second configurable logic in said second PLD to communicate a second signal,

where at least one of said first signal and said second signal or said first and second configurable logic in said first PLD or said first and second configurable logic in said second PLD are not the same.

2. The configurable hardware module of claim 1 wherein said PLD is a field programmable gate array.

3. The configurable hardware module of claim 1 wherein said PLD is selected from the group consisting of a non-programmable gate array (GA), a programmable gate array (PGA), a field programmable gate array (FPGA) a logical cell array (LCA) device, a programmable array logic (PAL) device, and a gate array logic (GAL) device.

4. The configurable hardware module of claim 1 wherein said private hardware resource is selected from the group consisting of an SRAM, a DRAM, a ROM, a register, a latch, non-volatile RAM and ferroelectric memory ROM.

5. The configurable hardware module of claim 1 wherein said configurable bus is a programmable I/O bus and further comprises a plurality of lines and means to seta said line to be selectively one of an input, output or bidirectional line, for transmitting signals at a specified voltage with specified timing characteristics.

6. An extensible processing unit comprising:

a plurality of interconnected modules, a first and a second of said modules each comprising;

a first and a second programmable logic device (PLD), each said PLD comprising a plurality of programmable pins for connection to one or more external devices and also comprising internal programmable interconnect and configurable logic, each of said programmable pins connectable through said programmable interconnect to said configurable logic;

a configurable bus connecting said first PLD and said second PLD, said configurable bus comprising a plurality of configurable bus lines, each of said configurable bus lines comprising a connection between a programmable pin on said first PLD and a corresponding programmable pin on said second PLD;

a private hardware resource directly connectible to said second PLD but not to said first PLD; and

a means for configuring said first PLD and said second PLD;

a second configurable bus comprising at least one configurable bus line connecting a programmable pin of a selected one of said first and said second PLDs of said first module to a programmable pin of a selected one of said first and said second PLDs of said second module, to allow communication between said PLDs;

whereby a said configurable bus line can be connected at a first time for communication between first configurable logic in a first connected PLD and first configurable logic in a second connected PLD to communicate a first signal and

connected at a second time for communication between second configurable logic in said first connected PLD and second configurable logic in said second connected PLD to communicate a second signal,

where at least one of said first signal and said second signal or said first and second configurable logic in said first connected PLD or said first and second configurable logic in said second connected PLD are not the same.

7. The extensible processing unit of claim 6 wherein said second configurable bus is a first programmable I/O bus, described as a module bus, also referred to as an M-bus.

8. The extensible processing unit of claim 6 further comprising

a third module comprising a first and a second PLD, a configurable bus, a private hardware resource directly connectible to said second PLD but not to said first PLD and a means for configuring said first PLD and said second PLD,

said second configurable bus further connecting together each of said first, second and third modules through a selected PLD on each module as a first programmable I/O bus, described as a module bus, also referred to as an M-bus,

a third configurable bus similar to said second configurable bus but connecting only said first module and said second module through at least one programmable pin of a PLD on each module as a second programmable I/O bus, described as a first neighborhood bus, also referred to as an N-bus and

a fourth configurable bus similar to said second configurable bus but connecting only said second module and said third module through at least one programmable pin of a PLD on each module as a third programmable I/O bus, a second neighborhood or N-bus.

9. The extensible processing unit of claim 7 further comprising a plurality of modules, each module being a distributed processing unit (DPU) comprising

a first and a second programmable logic device (PLD), each said PLD comprising a plurality of programmable pins for connection to one or more devices and also comprising internal programmable interconnect and configurable logic, at least one of said programmable pins connectable through said programmable interconnect to said configurable logic;

a configurable bus directly connecting said first PLD and said second PLD, said configurable bus comprising a plurality of configurable bus lines, each of said configurable bus lines comprising a connection between a programmable pin on said first PLD and a corresponding programmable pin on said second PLD;

a private hardware resource directly connectable to said second PLD but not to said first PLD; and

means for configuring said first PLD and said second PLD,

a plurality of programmable I/O buses connectable to said PLD second configurable bus is connected to a selected one of said first and second PLPs on each of a plurality of DPUs wherein each said DPU is connected to said plurality of other DPU units and to said bridge module through said M-bus.

10. The extensible processing unit of claim 7 further comprising

a host or external processing unit which is not part of said extensible processing unit, wherein said first module further comprises a bridge module, and

a third configurable bus similar to said second configurable bus connecting said first module and said second module through at least one programmable pin of a PLD on each module as a third programmable I/O bus, described as an H-bus, which is further connectable to said host or external processing unit.

11. A method of translating source code comprising the steps of:

providing source code in an algorithmic language; and

compiling said source code into a configuration file for implemenation on a processing device which supports in place;

wherein said processing device is a programmable logic device (PLD) and is one of a plurality of PLDs connectable through a programmable I/O connection, said PLD having connected private storage means for operators and connected private storage means for data storage, plus a programmable I/O connection to another PLD; and

wherein said private storage means for operators is a device, connectable to said PLD but to no other PLD, selected from the group consisting of a CPU, a serial computing device and a memory device; and

wherein said private storage means for data storage is a device, connectable to said PLD but to no other PLD, selected from the group consisting of a CPU, a serial computing device and a memory device.

12. The method of claim 11 wherein the step of compiling said source code further comprises sequential phases of:

a tokenizing phase;

a token mapping phase;

a logical mapping phase;

a logic optimization phase; and

a device specific mapping phase.

13. The method of claim 11 wherein said algorithmic language is selected from the group consisting of ABCL/1, ACL, Act I, Actor, ADA, ALGOL, Amber, Andorca-I, APL, AWK, BASIC, BCPL, BLISS, C, C++, C*, COBOL, ConcurrentSmallTalk, EULER, Extended FP, FORTH, FORTRAN, GHC, Id, IF1, JADE, LEX, Linda, LISP, LSN, Miranda, MODULA-2, OCCAM, Omega, Orient84/K, PARLOG, PASCAL, pC, PL/C, PL/I, POOL-T, Postscript, PROLOG, RATFOR, RPG, SAIL, Scheme, SETL, SIMPL, SIMULA, SISAL, Smalltalk, Smalltalk-80, SNOBOL, SQL, TEX, WATFIV and YACC.

14. The method of claim 13 wherein said algorithmic language is C or a derivative of C.

15. The method of claim 11 further comprising

providing a support configuration module including an function not available in said algorithmic language, said configuration module connectable to said processing device such that said executable function can be accessed by said processing device, and

compiling said source code for implementation in part using said executable function.

16. The method of claim 12 further comprising

providing a host computer connected to said processing device,

providing and using a first function to direct some program steps to execute on said processing device and some program steps to execute on said host computer,

providing a DSP connected to said PLD,

providing and using a a second function to direct some program steps to execute on said DSP,

compiling said source code to provide a plurality of program threads, two of said program threads capable of simultaneous execution,

providing and using a third function to allow said two program threads capable of simultaneous execution to execute simultaneously, and

providing and using a fourth function to allow control of the timing of one or more of said threads.

17. The method of claim 11 further comprising a stream splitter which selects source code which can be implemented on an available processing device and source code which should be implemented on a host computer connected to said processing device.

18. The method of claim 12 further comprising translating source code instructions selected from the group consisting of a C operator, a C expression, a thread control instruction, an I/O control instruction, and a hardware implementation instruction.

19. The method of claim 18 wherein said hardware implementation instruction is selected from the group consisting of pin assignments, handling configurable I/O buses, communication protocols between devices, clock generation, and host/module I/O.