Input/output processor with a local memory providing shared resources for a plurality of input/output interfaces on an I/O bus

• US 5,603,051 A
• Filed: 06/06/1995
• Issued: 02/11/1997
• Est. Priority Date: 06/06/1995
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Ezzet, Ali
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Chen, Duo
• Application Number:
  US08/472,795
• Time in Patent Office: 616 Days
• Field of Search: 395/200.01, 395/650, 395/823, 395/308, 395/822, 395/474
• US Class Current: 710/2
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Within a computing system, an input/output processor provides resources shared by several input/output interfaces. The computing system includes both a host bus and an input/output bus. One or more host processors are connected to the host bus. A bus bridge connects the input/output bus to the host bus. The bus bridge is used for transferring information between the host bus and the input/output bus. A first input/output interface provides an interface between a first external input/output system and the input/output bus. A second input/output interface provides an interface between a second external input/output system and the input/output bus. An input/output processor, also connected to the input/output bus, includes an embedded processor connected to a local memory. The input/output processor controls data transactions through the first input/output interface and controls data transactions through the second input/output interface. The local memory provides temporary storage for data transactions through the first input/output interface and for data transactions through the second input/output interface.

Claims

1. A computing system comprising:

a host bus;

a host processor, coupled to the host bus;

an input/output bus;

a bus bridge coupled between the input/output bus and the host bus, the bus bridge being used for transferring information between the host bus and the input/output bus;

a first input/output interface, connected to the input/output bus, which provides an interface between a first external input/output system and the input/output bus;

a second input/output interface, connected to the input/output bus, which provides an interface between a second external input/output system and the input/output bus; and

,

an input/output processor, connected to the input/output bus, the input/output processor including;

a local bus,

an embedded processor connected to the local bus, and

a local memory, connected to the local bus, the input/output processor controlling data transactions through the first input/output interface and the input/output processor controlling data transactions through the second input/output interface, the local memory providing temporary storage for data transactions through the first input/output interface and for data transactions through the second input/output interface.

2. A computing system as in claim 1 wherein a first data transfer between the first input/output interface and the second input/output interface is set up by control information transferred between the host processor and the embedded processor.

3. A computing system as in claim 2, wherein during the first data transfer, transferred data is stored in the local memory.

7. A computer system as in claim 1 additionally comprising:

a second input/output bus;

a second bus bridge coupled between the second input/output bus and the host bus, the second bus bridge being used for transferring information between the host bus and the second input/output bus; and

a third input/output interface, coupled to the second input/output bus, which provides an interface between a third external input/output system and the second input/output bus;

wherein the input/output processor, is also coupled to the second input/output bus, the input/output processor controlling data transactions through the third input/output interface, the local memory providing temporary storage for data transactions through the third input/output interface.

8. A computing system as in claim 7 wherein a first data transfer between the first input/output interface and the third input/output interface is set up by control information transferred between the host processor and the embedded processor.

9. A computing system as in claim 8, wherein during the first data transfer, transferred data is stored in the local memory.

10. A computing system as in claim 7 additionally comprising:

a main memory for the computing system comprising,

a first main memory segment coupled to the host bus, and

a second main memory segment, the second main memory segment being part of the local memory, wherein the first main memory segment and the second main memory segment are configured to appear to the host processor as a single logical memory image.

11. A computing system as in claim 1 wherein the input/output bus operates in accordance to a PCI bus standard.

4. A computing system as in claim I additionally comprising:

a main memory for the computing system comprising,

a first main memory segment coupled to the host bus, and

a second main memory segment, the second main memory segment being part of the local memory, wherein the first main memory segment and the second main memory segment are configured to appear to the host processor as a single logical memory image.

5. A computing system as in claim 4 wherein a first data transfer between the first input/output interface and the second input/output interface is set up by control information transferred between the host processor and the embedded processor.

6. A computing system as in claim 5, wherein during the first data transfer, transferred data is stored in the local memory.

12. In a computing system, a method for controlling data transfers over an input/output bus, comprising the steps of:

(a) setting up all data transfers to be performed over the input/output bus using an input/output processor, the input/output processor having a local bus, an embedded processor connected to the local bus, and a local memory connected to the local bus, step (a) including the following substep;

(a.1) sending control information sent between the input/output processor and a host processor connected to the host bus, the control information passing through a bus bridge connected between the input/output bus and the host bus; and

,

(b) for each data transfer set up in step (a), transferring data over the input/output bus between one of the plurality of input/output interfaces and the local memory within the input/output processor.

13. A method as in claim 12 additionally comprising the following step performed before step (a):

(c) configuring a first main memory segment connected to the host bus and a second main memory segment within the local memory to appear to an operating system for the computing system as a single logical memory image.

14. A computing system as in claim 12 wherein in step (a) and step (b) the input/output bus operates in accordance to a PCI bus standard.

15. In a computing system, a method for controlling data transfers over a first input/output bus and a second input/output bus, comprising the steps of:

(a) setting up all data transfers to be performed over the first input/output bus using an input/output processor, the input/output processor having a local bus, an embedded processor connected to the local bus, and a local memory connected to the local bus, step (a) including the following substep;

(a.1) sending control information between the input/output processor and a host processor connected to the host bus, the control information passing through a bus bridge connected between the first input/output bus and the host bus;

(b) setting up all data transfers to be performed over the second input/output bus using the input/output processor so that data transfers between one of a second plurality of input/output interfaces, connected to the second input/output bus, and the local memory within the input/output processor is set up by control information sent between the input/output processor and the host processor connected to the host bus;

(c) for each data transfer set up in step (a), transferring data over the first input/output bus between one of the first plurality of input/output interfaces and the local memory within the input/output processor; and

,

(d) for each data transfer set up in step (b), transferring data over the second input/output bus between one of the second plurality of input/output interfaces and the local memory within the input/output processor.

16. A method as in claim 15 additionally comprising the following step performed before step (a):

(e) configuring a first main memory segment connected to the host bus and a second main memory segment within the local memory to appear to an operating system for the computing system as a single logical memory image.

17. A computing system as in claim 15 wherein in steps (a) through (d) the first input/output bus and the second input/output bus operate in accordance to a PCI bus standard.