Interface circuit for transferring data between host and mass storage by assigning address in the host memory space and placing the address on the bus

• US 5,603,052 A
• Filed: 05/26/1995
• Issued: 02/11/1997
• Est. Priority Date: 10/20/1992
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Chejlava, Jr., Edward J., Cline, Leslie E., Curt, Kenneth C.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): MEKY, MOUSTAFA M
• Application Number:
  US08/451,877
• Time in Patent Office: 627 Days
• Field of Search: 395/821, 395/823, 395/824, 395/500, 395/800, 395/307, 395/309
• US Class Current: 710/4
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.

Claims

1. A method for transferring data from a host device to a mass storage device via an interface circuit, the host device being coupled to the interface circuit via a first parallel bus, the interface circuit being coupled to the mass storage device via a second parallel bus, the host device comprising a processor and memory, the processor of the host device having an IO space and a memory space, the method comprising the steps of:

(a) assigning an address in the memory space of the processor as a data port for transferring data between the host device and the interface circuit;

(b) storing the assigned address in the interface circuit;

(c) the processor executing memory instructions to transfer data from the processor via the first parallel bus to the interface circuit, the data being transferred into the interface circuit in response to the assigned address in the memory space being placed on the first parallel bus; and

(d) transferring the data from the interface circuit to the mass storage device via the second parallel bus.

2. The method of claim 1, wherein the mass storage device comprises a disk drive and wherein the second parallel bus is an IDE bus.

3. The method of claim 2, wherein the step of assigning an address involves assigning a range of addresses in the memory space.

4. The method of claim 2, wherein the processor of the host device is an 80×

86 family processor.

5. The method of claim 2, wherein the data is transferred from the processor to the interface circuit in 32-bit words and wherein the data is transferred from the interface circuit to the mass storage device in 16-bit words.

6. The method of claim 1, wherein step (c) further comprises the steps of:

the interface circuit detecting the assigned address in the memory space on the first parallel bus; and

the interface circuit providing control signals onto the first parallel bus to transfer the data from the first parallel bus into the interface circuit.

7. The method of claim 6, further comprising the steps of:

the interface circuit detecting a predetermined address in the IO space on the first parallel bus; and

transferring data from the first parallel bus into the interface circuit in response to the predetermined address in the IO space being placed on the first parallel bus, the processor executing IO instructions to transfer the data.

8. The method of claim 7, wherein the host device can selectably place the assigned address in the memory space on the first parallel bus or place the predetermined address in the IO space on the first parallel bus to transfer data from the host device to the interface circuit.

9. A method for transferring data from a mass storage device to a host device via an interface circuit, the host device being coupled to the interface circuit via a first parallel bus, the interface circuit being coupled to the mass storage device via a second parallel bus, the host device comprising a processor and memory, the processor of the host device having an IO space and a memory space, the method comprising the steps of:

(a) transferring data from the mass storage device to the interface circuit via the second parallel bus;

(b) assigning an address in the memory space of the processor as a data port for transferring data between the interface circuit and the host device;

(c) storing the assigned address in the interface circuit; and

(d) the processor executing memory instructions to transfer data from the interface circuit via the first parallel bus to the processor of the host device, the data being transferred out of the interface circuit in response to the assigned address in the memory space being placed on the first parallel bus.

10. The method of claim 9, wherein the mass storage device comprises a disk drive and wherein the second parallel bus is an IDE bus.

11. The method of claim 10, wherein the step of assigning an address involves assigning a range of addresses in the memory space.

12. The method of claim 10, wherein the processor of the host device is an 80×

86 family processor.

13. The method of claim 9, wherein the data is transferred from the mass storage device to the interface circuit in 16-bit words and wherein the data is transferred from the interface circuit to the processor in 32-bit words.