Interface circuit for transferring data between host and mass storage by assigning address in the host memory space and placing the address on the bus
First Claim
1. A method for transferring data from a host device to a mass storage device via an interface circuit, the host device being coupled to the interface circuit via a first parallel bus, the interface circuit being coupled to the mass storage device via a second parallel bus, the host device comprising a processor and memory, the processor of the host device having an IO space and a memory space, the method comprising the steps of:
- (a) assigning an address in the memory space of the processor as a data port for transferring data between the host device and the interface circuit;
(b) storing the assigned address in the interface circuit;
(c) the processor executing memory instructions to transfer data from the processor via the first parallel bus to the interface circuit, the data being transferred into the interface circuit in response to the assigned address in the memory space being placed on the first parallel bus; and
(d) transferring the data from the interface circuit to the mass storage device via the second parallel bus.
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Accused Products
Abstract
A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
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Citations
13 Claims
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1. A method for transferring data from a host device to a mass storage device via an interface circuit, the host device being coupled to the interface circuit via a first parallel bus, the interface circuit being coupled to the mass storage device via a second parallel bus, the host device comprising a processor and memory, the processor of the host device having an IO space and a memory space, the method comprising the steps of:
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(a) assigning an address in the memory space of the processor as a data port for transferring data between the host device and the interface circuit; (b) storing the assigned address in the interface circuit; (c) the processor executing memory instructions to transfer data from the processor via the first parallel bus to the interface circuit, the data being transferred into the interface circuit in response to the assigned address in the memory space being placed on the first parallel bus; and (d) transferring the data from the interface circuit to the mass storage device via the second parallel bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for transferring data from a mass storage device to a host device via an interface circuit, the host device being coupled to the interface circuit via a first parallel bus, the interface circuit being coupled to the mass storage device via a second parallel bus, the host device comprising a processor and memory, the processor of the host device having an IO space and a memory space, the method comprising the steps of:
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(a) transferring data from the mass storage device to the interface circuit via the second parallel bus; (b) assigning an address in the memory space of the processor as a data port for transferring data between the interface circuit and the host device; (c) storing the assigned address in the interface circuit; and (d) the processor executing memory instructions to transfer data from the interface circuit via the first parallel bus to the processor of the host device, the data being transferred out of the interface circuit in response to the assigned address in the memory space being placed on the first parallel bus. - View Dependent Claims (10, 11, 12, 13)
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Specification