Method for forming a multilayer integrated circuit

• US 5,604,137 A
• Filed: 06/02/1995
• Issued: 02/18/1997
• Est. Priority Date: 09/25/1991
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Mase, Akira, Takemura, Yasuhiko, Uochi, Hideki, Yamazaki, Shunpei
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/460,632
• Time in Patent Office: 627 Days
• Field of Search: 437/21, 437/40 TF, 437/41 TF, 437/34, 437/52, 437/56, 437/57, 437/915
• US Class Current: 438/153
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

Claims

1. A method for forming a semiconductor device comprising the steps of:

forming a first MOS transistor of one conductivity type on a semiconductor substrate;

forming an insulating film on said first MOS transistor;

selectively forming a semiconductor film on said insulating film;

forming an opening in said insulating film;

forming a gate electrode on said semiconductor film;

oxidizing a material of said gate electrode;

introducing an impurity into said semiconductor film to form a doped region therein; and

forming an electrode connecting said doped region with one of source and drain of said first MOS transistor,

wherein said electrode is in contact with top and side surfaces of said doped region.

2. The method of claim 1 wherein said a gate electrode comprises a multi-layer of a silicon film and an aluminum film provided on said silicon film.

3. The method of claim 1 wherein said a gate electrode comprises a multi-layer of an aluminum film and a tantalum film provided on said aluminum film.

4. The method of claim 1 wherein said a gate electrode comprises a single layer comprising a material selected from the group consisting of aluminum, tantalum, titanium, aluminum silicide, tantalum silicide and titanium silicide.

5. A method for forming a semiconductor device comprising:

a first MOS transistor of one conductivity type provided on a semiconductor substrate; and

a second MOS transistor of a conductivity type different from said one conductivity type provided on said first MOS transistor with an insulating film therebetween, said second MOS transistor comprising a gate electrode and an oxide layer covering a surface of said gate electrode,

said method comprising the steps of;

forming a semiconductor layer on said insulating film;

forming a gate insulating film on said semiconductor layer;

introducing an impurity into said semiconductor layer to form a doped region therein;

removing a portion of said gate insulating film to expose a portion of said doped region of said semiconductor layer with a portion of said semiconductor layer being unexposed under said gate electrode and said oxide layer;

forming a hole in the exposed portion; and

forming an electrode and a wiring connecting the exposed portion of said doped region with a terminal of said first MOS transistor through said hole,

wherein said electrode and said wiring are in contact with top and side surfaces of said doped region.

6. The method of claim 5 wherein a source or a drain of said second MOS transistor is provided in said exposed portion and is connected with said terminal through said hole.

7. The method of claim 5 wherein said terminal is a source or a drain terminal of said first MOS transistor.

8. The method of claim 5 wherein said gate electrode comprises a single layer comprising a material selected from the group consisting of aluminum, tantalum, titanium, aluminum silicide, tantalum silicide and titanium silicide.

9. The method of claim 5 wherein said gate electrode comprises a multi-layer of a silicon film and an aluminum film provided on said silicon film.

10. The method of claim 5 wherein said gate electrode comprises a multi-layer of an aluminum film and a tantalum film provided on said aluminum film.

11. A method for forming a semiconductor device comprising the steps of:

forming a first MOS transistor of one conductivity type on a semiconductor substrate;

forming an insulating film on said first MOS transistor;

selectively forming a semiconductor film on said insulating film;

forming an opening in said insulating film;

forming a gate electrode on said semiconductor film;

oxidizing a material of said gate electrode to form an oxidized surface of said gate electrode;

introducing an impurity into said semiconductor film to form a doped region therein; and

forming an electrode connecting said doped region with one of source and drain of said first MOS transistor,

wherein said electrode is in contact with top and side surfaces of said doped region, and

wherein said electrode crosses said gate electrode over the oxidized surface of said gate electrode.