Virtual interface representation of hierarchical symbolic layouts

• US 5,604,680 A
• Filed: 08/15/1994
• Issued: 02/18/1997
• Est. Priority Date: 08/15/1994
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Bamji, Cyrus, Varadarajan, Ravi
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/290,364
• Time in Patent Office: 918 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/118
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method and system provide for the symbolic design of a symbolic layout of an integrated circuit using only the topological features of the cells of the layout, absent geometrical information. Virtual leaf cells define circuit elements, and virtual hierarchical cells combine virtual leaf cells and other virtual hierarchical cells into hierarchical arrangements using interface graphs. Virtual interfaces describe the connectivity and orientation relations between virtual cells. The interfaces inherit the definitional requirements of interfaces at lower levels. The symbolic layout is produced from a hierarchy of virtual cells using hierarchical compaction and routing technology.

Claims

1. A method for symbolically representing a circuit layout comprised of a plurality of circuit elements, the circuit elements defined without geometrical values, the method comprising:

a) defining at least one virtual cell containing a topological constraint model of a plurality of circuit elements, a virtual cell being either a virtual leaf cell or a virtual hierarchical cell;

b) creating at least one instance of a virtual cell, the virtual cell being either a virtual leaf cell or a virtual hierarchical cell;

c) defining at least one virtual cell interface between a pair of virtual cells, and at least one connectivity relationship between the pair of virtual cells; and

d) coupling a pair of instances of virtual cells with a virtual cell interface.

2. The method of claim 1, wherein receiving a first user input defining at least one virtual cell containing a topological constraint model of a plurality of circuit elements, further comprises:

defining a virtual hierarchical cell using an interface graph containing instances of virtual cells and virtual cell interfaces coupling pairs of said instances.

3. The method of claim 1 wherein creating at least one instance of a virtual cell includes associating an orientation with the instance of the virtual cell.

4. The method of claim 1, further comprising:

e) repeating steps a) through d) for any number of virtual cells and virtual cell interfaces.

5. The method of claim 1, wherein defining at least one virtual cell interface, further comprises:

defining a virtual leaf cell interface identifying a pair of virtual leaf cells, and at least one pin binding pair coupling the virtual leaf cells.

6. The method of claim 5 wherein defining a virtual leaf cell interface includes associating with said interface an orientation that satisfies any pin binding considerations of the interface.

7. The method of claim 5 wherein defining a virtual leaf cell interface includes associating an interface type with the interface.

8. The method of claim 7 wherein the interface type is either abutting or routing.

9. The method of claim 1, wherein defining at least one virtual cell interface, further comprises:

defining a virtual hierarchical cell interface identifying a pair of instances of virtual cells and a virtual cell interface coupling said instances.

10. The method of claim 9 wherein defining a virtual hierarchical cell interface includes associating with the interface an orientation that is consistent with any orientations of interfaces used to define the virtual hierarchical cell interface.

11. The method of claim 1 further comprising:

compacting the circuit layout using hierarchical compaction techniques to determine placement information for each circuit element and each instance of a virtual cell in the circuit layout.

12. In a computer system for the automated design of electrical circuits including a library of stored leaf cells representative of primitive circuit elements and hierarchical cells, a memory unit for storing data, a processor, and a layout database for storing a symbolic circuit layout having a plurality of cells, a design tool, stored in the memory unit and executable by the processor for symbolically representing the circuit layout, comprising:

a first means, operatively coupled to the library, for receiving therefrom a stored cell, and defining a virtual cell from the stored cell and storing the virtual cell in the memory unit;

a second means for defining and storing in the memory unit a virtual cell interface;

a third means, operatively coupled to the memory unit for retrieving a virtual cell therefrom for creating and storing in the memory unit an instance of the virtual cell in the layout database; and

a fourth means operatively coupled to the layout database for coupling instances of virtual cells, and storing the coupling in the memory unit, wherein the processor is operatively controlled by the first, second, third and fourth means in response to user specification.

13. The design tool of claim 12, wherein the first means further comprises:

means for defining and storing in the memory unit a virtual leaf cell containing a topological constraint model of a primitive circuit element stored in the library of leaf cells.

14. The design tool of claim 12, wherein the second means further comprises:

means for defining and storing in the memory unit a virtual leaf cell interface identifying a pair of virtual leaf cells, and at least one pin binding pair; and

means for defining and storing in the memory unit a virtual hierarchical cell interface using an interface graph containing instances of virtual cells and virtual interfaces coupling pairs of said instances.

15. The system of claim 12, wherein the first means further comprises:

means for defining and storing in the memory unit a virtual hierarchical cell using an interface graph containing either a) instances of virtual leaf cells and virtual leaf cell interfaces coupling pairs of said instances, or b) virtual hierarchical cells and a virtual hierarchical cell interface coupling said instances.

16. In a computer system for the automated design of electrical circuits including a processor, a cell library of stored cells representative of circuit elements, a layout database for storing a symbolic circuit layout having a plurality of cells, a plurality of memories, a design tool for symbolically representing the circuit layout using virtual cells including virtual leaf cells and virtual hierarchical cells, the design tool comprising:

a virtual cell extractor, executable by the processor for creating a virtual cell containing a topological constraint model from a cell stored in the cell library, virtual cell extractor storing the virtual cell in a virtual cell memory;

a virtual instance creator, executable by the processor for creating an instance of a virtual cell and storing said instance in the layout database;

a virtual instance connector, executable by the processor for connecting a pair of instances of virtual cells with a virtual cell interface; and

a virtual cell interface creator, executable by the processor for defining a virtual cell interface between a pair of virtual cells.

17. The design tool of claim 16, wherein the virtual cell extractor further creates from a hierarchical cell stored in the cell library a virtual hierarchical cell using an interface graph to represent cells and interfaces connecting the cells in the hierarchical cell.

18. The design tool of claim 16, wherein the virtual interface creator defines a virtual leaf cell interface between a pair of virtual leaf cells, the virtual leaf cell interface including at least one pin binding pair between the virtual leaf cells, and an orientation of one virtual leaf cell with respect to the other virtual leaf cell.

19. The design tool of claim 16, wherein the virtual interface creator defines a virtual hierarchical interface between a pair of virtual hierarchical cells, the virtual hierarchical interface including at least one pair of virtual cells coupled by a virtual interface.

20. In a computer system for the automated design of an electrical circuit, a cell library including a plurality of stored cells representative of circuit elements, at least one stored cell comprising:

an interface graph containing selected instances of non-primitive circuit elements, the interface graph defining a set of connectivity constraints between the selected instances.

21. A method for symbolically forming a leaf cell comprised of selected circuit objects, the method consisting of the steps of:

a) receiving a first input selecting circuit objects;

b) receiving a second input defining a connectivity relationship between the selected circuit objects;

c) receiving a third user input defining spacing constraints between the selected circuit objects to define a circuit element;

d) defining an interface relationship between at least one pair of circuit elements;

f) forming at least one hierarchical circuit element from at least one set of circuit elements; and

g) defining an interface relationship between at least one pair of hierarchical circuit elements.

22. A computer system for the automated design of electrical circuits and for symbolically representing the circuit layout, the system comprising:

a stored library of stored leaf cells representative of primitive circuit elements;

a layout database for storing a symbolic circuit layout having a plurality of cells;

a memory unit for storing data;

means for defining and storing in the memory unit a virtual leaf cell containing a topological constraint model of a primitive circuit element stored in the library of leaf cells;

means for defining and storing in the memory unit a virtual leaf cell interface identifying a pair of virtual leaf cells, and at least one pin binding pair;

means for creating and storing in the memory unit an instance of a virtual leaf cell in the layout database;

means for coupling instances of virtual leaf cells, and storing the coupling in the memory unit;

means for defining and storing in the memory unit a virtual hierarchical cell using an interface graph containing either a) instances of virtual leaf cells and virtual leaf cell interfaces coupling pairs of said instances, or b) virtual hierarchical cells and a virtual hierarchical cell interface coupling said instances;

means for creating and storing an instance of a virtual hierarchical cell in the layout database;

means for coupling instances of virtual hierarchical cells, and storing the coupling in the memory unit; and

a processor operatively coupled to the library, the database, the memory unit, for selectively retrieving therefrom and storing selectively therein virtual cells, and virtual interfaces.