Embedded programmable sensor calibration method

• US 5,604,684 A
• Filed: 12/30/1993
• Issued: 02/18/1997
• Est. Priority Date: 12/30/1993
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Juntunen, Robert D.
• Primary Examiner(s): Ramirez, Ellis B.
• Assistant Examiner(s): CHOI, KYLE JAEHUN
• Application Number:
  US08/175,908
• Time in Patent Office: 1,146 Days
• Field of Search: 364/571.04, 364/571.05, 364/442, 364/483, 364/571.07, 73/1 R, 73/1 D, 73/1 B, 73/3, 454/229, 219/378
• US Class Current: 702/104
• CPC Class Codes: G01D 3/022 having an ideal characteristic, map or correction data stored in a digital memory
• CPC Class Codes: G01F 25/10 of flowmeters
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method for quick and low cost calibration of a sensor to remove span and offset errors. Span and offset errors are removed using a circuit which produces a corrected output signal as a function of calculated gain and offset values. The gain and offset values are calculated by first measuring an uncorrected sensor output at no input and at full scale output. These values are then used in an equation to calculate offset and gain values. The circuit includes an amplifier, a switch, a gain circuit, an offset circuit and a memory. The memory, which may be serial written memory including static RAM and a shift register, stores gain and offset coefficients for use by the gain and offset circuits and the amplifier. The gain and offset circuits may include digital to analog converters for converting the stored gain and offset digital values into analog equivalents.

Claims

1. A method for establishing a voltage level for an output signal from a sensor and its associated correction circuit, the sensor having a desired null output level achieved by said correction circuit that is substantially equal to Vo2 and a desired full scale output equal to Vo1, said Vo1 and Vo2 levels being the approximate range of acceptable input to an analog to digital converter that accepts output from said correction circuit, the correction circuit comprising an amplifier having first and second input ports and an output port said output port supplying said output level as its output, and a resistance R1 connected to provide an offset signal to said second input port, the sensor being connected to the first input port, wherein the method for providing a voltage value for said offset signal comprises the steps of:

(a) connecting the sensor output to a measurement device so as to be able to measure the output signal of the sensor at a zero stimulus level (named Vlo) and at a full scale level (named Vhi), said connection to a measurement device being named a measurement configuration;

(b) measuring the output signal of the sensor at both Vlo and Vhi;

(c) based on these measurements, determining the offset voltage value (named Vr) by calculating the relationship defined as;

space="preserve" listing-type="equation">Vr=(Vhi*Vo2-Vlo*Vo1)/(Vhi-Vo1-Vlo+Vo2);

(d) based again on these measurements and the determined Vr, determining a gain voltage value (named gain'"'"') for correcting the sensor output signal for span error using the equations;

space="preserve" listing-type="equation">Rf=((Vhi-Vo1)*R1)/(Vr-Vhi)

space="preserve" listing-type="equation">gain'"'"'=Rf/R1;

(e) configuring the correction circuit to apply said gain voltage and said offset voltage values to said first input port of said amplifier; and

(f) disconnecting the sensor output from said measurement device.

2. The method of claim 1 wherein said correction circuit further includes a pre-amplifier having input ports connected to the sensor and an output terminal connected to the first input port of the amplifier, and a switch means connected to the output ports of the pre-amplifier and the amplifier and the input port of a processor to determine said values in said measurement configuration, comprising the further steps of:

(g) enabling the output port of the preamplifier and disabling the output port of the amplifier so that only a pre-amplified signal is used by the processor at least during steps (a) and (b); and

(h) enabling the output port of the amplifier and disabling the output port of the pre-amplifier for at least step (f).

3. The method of claim 2, wherein the correction circuit further comprises memory which can be loaded with values corresponding to the determined values, a shift register connected to the memory, and a gain and offset digital to analog converter circuit connected to receive output from said shift register and deliver output to said first input port of said amplifier, comprising the further steps of:

(g) storing a digital equivalent of said determined values in the memory; and

(h) sending through said shift registers said digital equivalents to the offset and gain digital to analog converter circuit to produce analog offset and gain values; and

(i) applying said analog offset and gain values to said first input port of said amplifier.

4. The method of claim 1, wherein the correction circuit further comprises memory which can be loaded with values corresponding to the determined values, a shift register connected to the memory, and a gain and offset digital to analog converter circuit connected to receive output from said shift register and deliver output to said first input port of said amplifier, comprising the further steps of:

(g) storing a digital equivalent of said determined values in the memory; and

(h) sending through said shift registers said digital equivalents to the offset and gain digital to analog converter circuits to produce analog offset and gain values; and

(i) applying said analog offset and gain values to said first input port of said amplifier.