Persistent data storage which utilizes a shared power supply

• US 5,604,709 A
• Filed: 08/07/1995
• Issued: 02/18/1997
• Est. Priority Date: 08/07/1995
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Price, Noah M.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/512,180
• Time in Patent Office: 561 Days
• Field of Search: 365/229, 365/226, 365/154, 364/707, 371/66
• US Class Current: 365/229
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A relatively inexpensive static random access memory is utilized to store persistent data in a computer. To provide the SRAM with this capability, it is connected to a source of power within the computer that includes a battery. The source of power is connected to the SRAM in a manner such that the SRAM is in an enabled state whenever any power is available to it, from either a battery or a power supply connected to a regulated voltage source. When the computer is turned off, to prevent devices connected to the SRAM from draining current being provided by the battery, a chip select terminal of the SRAM is isolated from other circuits on the computer, to prevent leakage.

Claims

1. An electronic memory circuit for the storage of persistent data, comprising:

a memory device having a select terminal for receiving a signal which controls the memory to selectively permit data to be read therefrom and having an enable terminal for coupling a supply voltage;

a source of power for supplying said supply voltage in at least two different states including a normal operating state and a standby state, said supply voltage being inversely coupled to said select terminal with respect to said enable terminal; and

a switch responsive to the state of said power source for selectively isolating said select terminal from a source of said signal when said power source is in said standby state.

2. The memory circuit of claim 1 further including means for connecting said power source to said select terminal to normally inhibit data from being read from said memory device.

3. The memory circuit of claim 1 wherein, during said normal operating state, power is supplied to said memory device and to other electrical components to which said memory device is connected.

4. The memory circuit of claim 3 wherein, during said standby state, power is not supplied to said other electrical components.

5. The memory circuit of claim 4 wherein, during said standby state, power is supplied to said memory device from a battery.

6. The memory circuit of claim 4 wherein, during said standby state, power is supplied to said memory device as a trickle charge from a regulated power supply.

7. The memory circuit of claim 1 wherein said memory device is a static random access memory.

8. The memory circuit of claim 1 wherein said switch is an FET.

9. A method for using a static random access memory to store persistent data comprising the steps of:

providing a continuous supply of power to an enable terminal of said memory in a normal state or a standby state;

connecting the supply of power to a select terminal of said memory to normally inhibit data from being read from or written into said memory;

applying a select signal to said select terminal to permit data to be read from and written into said memory; and

selectively isolating said select terminal from a source of said select signal in dependence upon whether said supply of power is in said normal state or said standby state.

10. The method of claim 9 wherein said select terminal is isolated from said signal source when said supply of power is in said standby state.

11. The method of claim 9 wherein the step of supplying power during said normal state includes supplying power to other electrical components to which said memory is connected.

12. The method of claim 11 wherein, during said standby state, power is not supplied to said other electrical components.

13. The method of claim 12 wherein power is supplied to said memory from a battery during said standby state.

14. The method of claim 12 wherein power is supplied to said memory as a trickle charge from a regulated power supply during said standby state.