Frequency synchronized bidirectional radio system

• US 5,604,768 A
• Filed: 12/21/1994
• Issued: 02/18/1997
• Est. Priority Date: 01/09/1992
• Status: Expired due to Term

• Current Assignee: Landis+Gyr Innovations Incorporated (Landis+Gyr Group AG)
• Original Assignee: CellNet Data Systems, Inc. (Landis+Gyr Group AG)
• Inventors: Fulton, Forrest F.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/361,799
• Time in Patent Office: 790 Days
• Field of Search: 375/219, 375/220, 375/221, 375/317, 375/358, 375/324, 375/326, 375/356, 455/51.1, 455/75, 455/76, 455/88, 327/50, 327/73, 327/77, 370/85.8, 370/95.2, 370/100.1
• US Class Current: 375/220
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency
• CPC Class Codes: H04B 1/56 with provision for simultaneous communication in two directions
• CPC Class Codes: H04B 7/2675 Frequency synchronisation
• CPC Class Codes: H04J 1/065 Synchronisation of carrier sources at the receiving station with the carrier source at the transmitting station
• CPC Class Codes: H04L 2027/0028 at passband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier
• CPC Class Codes: H04L 27/3854 using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase

Abstract

A bidirectional radio system for low-cost high-throughput accumulation of data from a large number of site units. Frequency synchronization is achieved at low cost by transmitting a high accuracy carrier and clock signal at a base station, and using receiving circuitry at remote stations to extract the base clock signal and base carrier frequency and a phase-lock loop to stabilize the remote station carriers. A burst demodulator at a base station receiver can decode a short remote station response by scaling the response with the phase and amplitude of an initial segment of the response. The burst demodulator may continuously update the decoding threshold based on a comparison of the signal amplitude and the current value of the decoding threshold. In an alternate embodiment, the carrier synthesizer is not part of a phase-lock loop, but the transmitted signal is rotated by a phase proportional to a frequency error to provide an accurate carrier frequency. In yet another alternate embodiment only a frequency-control loop is implemented, and again the transmitted signal is rotated by a phase ramp proportional to a frequency error to provide an accurate carrier frequency. In this embodiment separate rotators may be used on both the transmission and reception sides of the circuit, or a single rotator may be switched between the transmission and reception sides of the circuit for half-duplex operation.

Claims

1. An apparatus for decoding an encoded analog signal suffering from amplitude modulation to determine discrete output values, said discrete output values including a first nonzero value and a zero value, comprising:

a first means for comparing a first component of said encoded analog signal to a threshold value, if said first component is greater than said threshold value then said first means for comparing sets a first one of said discrete output values equal to said first nonzero value, and if said first component of said encoded analog signal is less than said threshold value then said first means for comparing sets said first one of said discrete output values equal to one of a set of discrete values, said set of discrete values including a zero value; and

a first means for modifying said threshold value by adding a first error signal multiplied by a first reduction factor thereto, if said first one of said discrete output values is said zero value then said first means for modifying sets said first error signal equal to zero, and if said first one of said discrete output values is said first nonzero value then said first means for modifying sets said first error signal equal to a difference between said first component of said encoded analog signal and twice said threshold value.

2. The apparatus of claim 1 wherein said set of discrete values includes a second nonzero value equal to a negative of said first nonzero value, if said first component of said encoded analog signal is less than a negative of said threshold value then said first means for comparing sets said first one of said discrete output values equal to said second nonzero value, if said first component of said encoded analog signal is greater than said negative of said threshold value and less than said threshold value then said first means for comparing sets said first one of said discrete output values equal to said zero value, and if said first one of said discrete output values is said second nonzero value then said first means for modifying sets said first error signal equal to a difference between an absolute value of said first component of said encoded analog signal and twice said threshold value.

3. The apparatus of claim 2 further comprising:

a second means for comparing a second component of said encoded analog signal to said threshold value, if said second component is greater than said threshold value then said second means for comparing sets a second one of said discrete output values equal to said first nonzero value, if said second component of said encoded analog signal is less than said negative of said threshold value then said second means for comparing sets said second one of said discrete output values equal to said second nonzero value, and if said second component of said encoded analog signal is greater than said negative of said threshold value and less than said threshold value then said second means for comparing sets said second one of said discrete output values equal to said zero value; and

a second means for modifying said threshold value by adding a second error signal multiplied by a second reduction factor thereto, if said second one of said discrete output values is said zero value then said second means for modifying sets said second error signal equal to zero, if said second one of said discrete output values is said first nonzero value then said second means for modifying sets said second error signal equal to a difference between said second component of said encoded analog signal and twice said threshold value, and if said second one of said discrete output values is said second nonzero value then said second means for modifying sets said second error signal equal to a difference between an absolute value of said second component of said encoded analog signal and twice said threshold value.

4. The apparatus of claim 3 wherein said first reduction factor is equal to said second reduction factor.

5. The apparatus of claim 1 further comprising a means for scaling an unscaled signal to provide said encoded analog signal by calculating an amplitude and phase of a reference segment of said unscaled signal to generate a scaling amplitude and a scaling phase, and scaling said amplitude and said phase of said unscaled signal by said scaling amplitude and said scaling phase, respectively.

6. A bidirectional radio communication system comprised of at least one communication cell, said cell having a base station and at least one remote station, said remote station receiving a polling signal at a base clock rate on a base carrier frequency from said base station, said remote station transmitting a response signal carrying a baseband response data signal with a remote clock rate to said base station, said remote station being comprised of:

a first frequency synthesizer generating a remote carrier frequency;

a first frequency heterodyne, said first heterodyne heterodyning said remote carrier frequency and polling signal to generate an intermediate frequency signal;

a second frequency synthesizer generating an intermediate frequency sinusoid, said intermediate frequency sinusoid being stabilized by a first frequency stabilization signal;

a second frequency heterodyne, said second heterodyne heterodyning said intermediate frequency sinusoid and said intermediate frequency signal to generate a received baseband signal;

a first recovery circuit, said first recovery circuit determining a frequency error signal related to a difference between said base carrier frequency and said remote carrier frequency;

a second recovery circuit, said second recovery circuit generating said first frequency stabilization signal and said remote clock rate from said base clock rate;

a rotator for rotating said baseband response data signal by a rate proportional to said frequency error signal to provide a frequency translated signal; and

a modulator for modulating said frequency translated signal onto said remote carrier frequency to provide said response signal.

7. The bidirectional radio communication system of claim 6 wherein said first frequency synthesizer utilizes said frequency error signal from said first recovery circuit in a frequency-control loop.

8. A bidirectional radio communication system comprised of at least one communication cell, said cell having a base station and at least one remote station, said remote station operating in half-duplex mode, said remote station receiving a polling signal at a base clock rate on a base carrier frequency from said base station during a reception, said remote station transmitting a response signal carrying a baseband response signal with a remote clock rate to said base station during a transmission, said remote station being comprised of:

a first frequency synthesizer generating a remote carrier frequency, and utilizing a frequency error signal in a frequency-control loop;

a first frequency heterodyne, said first heterodyne heterodyning said remote carrier frequency and said polling signal to generate an intermediate frequency signal;

a second frequency synthesizer generating an intermediate frequency sinusoid, said intermediate frequency sinusoid being stabilized by a first frequency stabilization signal;

a second frequency heterodyne, said second heterodyne heterodyning said intermediate frequency sinusoid and said intermediate frequency signal to generate a received baseband signal;

a first recovery circuit, said first recovery circuit including

a rotator for frequency-translating an input signal at a rotator input to provide a frequency-translated rotator output signal at a rotator output,

a phase detector for producing a phase detector output proportional to a phase of a phase detector input,

a ramp estimator for providing a rotator control signal to said rotator and producing said frequency error signal, said frequency error signal being related to a difference between said base carrier frequency and said remote carrier frequency,

a rotator input switch for directing said received baseband signal to said rotator input during said reception, and directing said baseband response signal to said rotator input during said transmission,

a rotator output switch for directing said rotator output to said phase detector input and a clock estimator input during said reception, and directing said rotator output to a modulator for modulating said rotator output onto said remote carrier frequency to provide said response signal during said transmission,

a ramp estimator input switch for connecting said phase detector output to said ramp estimator during said reception, and disconnecting said ramp estimator during said transmission so that said rotator control signal and said frequency error signal are unchanged, and

a clock estimator for determining an estimate of said base clock rate from said clock estimator input; and

a second recovery circuit, said second recovery circuit generating said first frequency stabilization signal and said remote clock rate from said estimate of said base clock rate.