Digital phase locked loop having coarse and fine stepsize variable delay lines

• US 5,604,775 A
• Filed: 09/29/1995
• Issued: 02/18/1997
• Est. Priority Date: 09/29/1994
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Saitoh, Tetsuo, Kitamura, Koichi, Matsuo, Syuji, Taniyoshi, Itsurou
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): KIM, KEVIN
• Application Number:
  US08/536,989
• Time in Patent Office: 508 Days
• Field of Search: 375/373, 375/374, 375/376, 327/147, 327/149, 327/156, 327/158, 348/536, 348/537, 331/25
• US Class Current: 375/376
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector. The up-down count value is supplied as the higher and lower significant bits to the coarse and fine stepsize variable delay lines at such longer intervals than the intervals at which the reference clock pulse occurs, so that the delayed clock pulse is allowed a sufficient time to propagate through the clock tree.

Claims

1. A digital phase locked loop for use with a clock tree having an input and a plurality of clock propagation paths extending from the input to a plurality of outputs, comprising:

a coarse stepsize variable delay line and a fine stepsize variable delay line connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits applied to the coarse stepsize delay line and in accordance with lower significant bits applied to the fine stepsize delay line, and delivering the delayed clock pulse to the input of said clock tree;

a phase detector for detecting a phase difference between the reference clock pulse and delayed clock pulse appearing at one of the outputs of the clock tree; and

delay control means for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with an output of said phase detector and supplying the count value as said higher and lower significant bits to said coarse and fine stepsize variable delay lines at longer intervals than intervals at which said reference clock pulse occurs so that said delayed clock pulse is allowed a sufficient time to propagate through said clock tree,

said delay control means including;

a first time counter for counting said reference clock pulse to produce a count and producing a first timing pulse when the count repeatedly reaches a predetermined value, said first timing pulse defining the start timing of each of said longer intervals;

a sequence controller responsive to a first occurrence of said first timing pulse for producing a first enable pulse when the output of said phase detector has a first logic level, and responsive to a repeated occurrence of said first timing pulse for producing a second enable pulse when the output of said phase detector has changed to a second logic level;

an up-down counter arranged to be enabled in response to said first and second enable pulses for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with a phase comparison provided by said phase detector, and producing from the count value a first group of delay control bits in response to said first enable pulse, and a second group of delay control bits and a third group of delay control bits in response to said second enable pulse;

a second timing counter responsive to each occurrence of said first timing pulse for counting a delayed clock pulse from said coarse stepsize delay line to produce a count, and producing a second timing pulse when the count reaches a predetermined value, said second timing pulse defining the end timing of each of said longer intervals; and

a latch, responsive to said second timing pulse, for latching and forwarding the first and second groups of delay control bits to said coarse stepsize delay line as said higher significant bits and latching and forwarding the third group of control bits to said fine stepsize delay line as said lower significant bits.

3. A digital phase locked loop as claimed in claim 1, wherein said up-down counter includes means for producing an overflow output for resetting said sequence controller to an initialized state when the count value of the up-down counter reaches a full count.

4. A digital phase locked loop as claimed in claim 3, wherein said sequence controller includes means responsive to said overflow output for causing said up-down counter To be initialized to a reset state for a period sufficients for the delayed clock pulse to propagate through said clock tree and starting to produce said enable pulses at the end of said period.

5. A digital phase locked loop as claimed in claim 3, wherein said first timing counter is arranged to be loaded with a second full count value when a first full count is reached after said sequence controller is reset to said initialized state, said first timing counter subsequently producing said first timing pulse when said load second full count is reached, said second full count value being smaller than said first full count value.

9. A digital phase locked loop as claimed in claim 1, wherein said up-down counter includes:

a first internal counter for counting the reference dock pulse to produce a first count value, incrementing or decrementing the first count value in accordance with said phase comparison, and producing from the first count value said third group of delay control bits, said first internal counter being arranged to be loaded with a first value when the first internal counter produces a carry output and a second value when the first internal counter produced a borrow output; and

a second internal counter for counting the reference clock pulse to produce a second count value, incrementing or decrementing the second count value in accordance with said phase comparison, and producing from the second count value said first and second groups of delay control bits in response to one of said carry and borrow outputs.

2. A digital phase locked loop for use with a clock tree having an input and a plurality of clock propagation paths extending from the input to a plurality of outputs, comprising:

a coarse stepsize variable delay line and a fine stepsize variable delay line connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits applied to the coarse stepsize delay line and in accordance with lower significant bits applied to the fine stepsize delay line, and delivering the delayed clock pulse to the input of said clock tree;

a phase detector for detecting a phase difference between the reference clock pulse and delayed clock pulse appearing at one of the outputs of the clock tree; and

delay control means for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with an output of said phase detector and supplying the count value as said higher and lower significant bits to said coarse and fine stepsize variable delay lines at longer intervals than intervals at which said reference clock pulse occurs so that said delayed clock pulse is allowed a sufficient time to propagate through said clock tree,

said delay control means including;

a first timing counter for counting said reference clock pulse to produce a count and producing a first timing pulse when the count repeatedly reaches a predetermined value, said first timing pulse defining the start timing of each of said longer intervals;

a sequence controller responsive to a first occurrence of said first timing pulse for producing a first enable pulse when the output of said phase detector has a first logic level or a second logic level, responsive to a repeated occurrence of said first timing pulse for producing a second enable pulse when the output of said phase detector has changed from said first or second logic level to the second or first level, respectively, and responsive to a further repeated occurrence of said first timing pulse for producing a third enable pulse when the output of said phase detector has changed from the logic level at which said second enable pulse was produced;

an up-down counter arranged to enable in response to said first, second and third enable pulses for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with a phase comparison provided by said phase detector, and producing from the count value a first group of delay control bits in response to said first enable pulse, a second group of delay control bits in response to said second enable pulse and a third group of delay control bits and a fourth group of delay control bits in response to said third enable pulse;

a second timing counter responsive to each occurrence of said first timing pulse for counting a delayed clock pulse from said coarse stepsize delay line to produce a count, and producing a second timing pulse when the count reaches a predetermined value, said second timing pulse defining the end timing of each of said longer intervals; and

a latch, responsive to said second timing pulse, for latching and forwarding a first, second and third groups of delay control bits to said coarse stepsize delay line as said higher significant bits and latching and forwarding the fourth group of control bits to said fine stepsize delay line as said lower significant bits.

6. A digital phase locked loop as claimed in claim 2, wherein said up-down counter includes means for producing an overflow output for resetting said sequence controller to an intialized state when the count value of the up-down counter reaches a full count.

7. A digit phase locked loop as claimed in claim 6, wherein said sequence controller includes means responsive to said overflow output for causing said up-down counter to be initialized to a reset state for a period sufficient for the delayed clock pulse to propagate through said clock tree and starting to produce said enable pulses at the end of said period.

8. A digital phase locked loop as claimed in claim 7, wherein said first timing count is arranged to be loaded with a second full count value when a first full count is reached after said sequence controller is reset to said initialized state, said first timing counter subsequently producing said first timing pulse when said loaded second full count is reached, said second full count value being smaller than said first full count value.

10. A digital phase locked loop as claimed in claim 2, wherein said up-down counter includes:

a first internal counter for counting the reference clock pulse to produce a first count value, incrementing or decrementing the first count value in accordance with said phase comparison, and producing from the first count value said fourth group of delay control bits, said first internal counter being arranged to be loaded with a first value when the first internal counter produces a carry output and a second value when the first internal counter produces a borrow output;

a second internal counter for counting the reference clock pulse to produce a second count value, incrementing or decrementing the second count value in accordance with said phase comparison, and producing from the second count value a lower significant subgroup of said second and third group, of delay control bits in response to each one of said carry and borrow outputs of internal counter; and

a third internal counter for counting the reference clock pulse to product a third count value, incrementing or decrementing the third count value in accordance with said phase comparison, and producing from the third count value said first group of delay control bits and a higher significant subgroup of said third group of delay control bits in response to a carry or a borrow output produced by said second internal counter.

11. A digital phase locked loop for use with a clock tree having an input and a plurality of clock propagation paths extending from the input to a plurality of outputs, comprising:

a coarse stepsize variable delay line and a fine stepsize variable delay line connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits applied to the coarse stepsize delay line and in accordance with lower significant bits applied to the fine stepsize delay line, and delivering the delayed clock pulse to the input of said clock tree;

a phase detector for detecting a phase difference between the reference clock pulse and delayed clock pulse appearing at one of the outputs of the clock tree; and

delay controller to count the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with an output of said phase detector and supplying the count value as said higher and lower significant bits to said coarse and fine stepsize variable delay lines at longer intervals than intervals at which said reference clock pulse occurs so that said delayed clock pulse is allowed a sufficient time to propagate through said clock tree,

said delay controller including;

a first time counter for counting said reference clock pulse to produce a count and producing a first timing pulse when the count repeatedly reaches a predetermined value, said first timing pulse defining the start timing of each of said longer intervals;

a sequence controller responsive to a first occurrence of said first timing pulse for producing a first enable pulse when the output of said phase detector has a first logic level, and responsive to a repeated occurrence of said first timing pulse for producing a second enable pulse when the output of said phase detector has changed to a second logic level;

an up-down counter arranged to be enabled in response to said first and second enable pulses for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with a phase comparison provided by said phase detector, and producing from the count value a first group of delay control bits in response to said first enable pulse, and a second group of delay control bits and a third group of delay control bits in response to said second enable pulse;

a second timing counter responsive to each occurrence of said first timing pulse for counting a delayed clock pulse from said coarse stepsize delay line to produce a count, and producing a second timing pulse when the count reaches a predetermined value, said second timing pulse defining the end timing of each of said longer intervals; and

a latch, responsive to said second timing pulse, for latching and forwarding the first and second groups of delay control bits to said coarse stepsize delay line as said higher significant bits and latching and forwarding the third group of control bits to said fine stepsize delay line as said lower significant bits.

12. A digital phase locked loop for use with a clock tree having an input and a plurality of clock propagation paths extending from the input to a plurality of outputs, comprising:

a coarse stepsize variable delay line and a fine stepsize variable delay line connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits applied to the coarse stepsize delay line and in accordance with lower significant bits applied to the fine stepsize delay line, and delivering the delayed clock pulse to the input of said clock tree;

a phase detector for detecting a phase difference between the reference clock pulse and delayed clock pulse appearing at one of the outputs of the clock tree; and

delay controller for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with an output of said phase detector and supplying the count value as said higher and lower significant bits to said coarse and fine stepsize variable delay lines at longer intervals than intervals at which said reference clock pulse occurs so that said delayed clock pulse is allowed a sufficient time to propagate through said clock tree,

said delay controller including;

a first timing counter for counting said reference clock pulse to produce a count and producing a first timing pulse when the count repeatedly reaches a predetermined value, said first timing pulse defining the start timing of each of said longer intervals;

a sequence controller responsive to a first occurrence of said first timing pulse for producing a first enable pulse when the output of said phase detector has a first logic level or a second logic level, responsive to a repeated occurrence of said first timing pulse for producing a second enable pulse when the output of said phase detector has changed from said first or second logic level to the second or first level, respectively, and responsive to a further repeated occurrence of said first timing pulse for producing a third enable pulse when the output of said phase detector has changed from the logic level at which said second enable pulse was produced;

an up-down counter arranged to enable in response to said first, second and third enable-pulses for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with a phase comparison provided by said phase detector, and producing from the count value a first group of delay control bits in response to said first enable pulse, a second group of delay control bits in response to said second enable pulse and a third group of delay control bits and a fourth group of delay control bits in response to said third enable pulse;

a second timing counter responsive to each occurrence of said first timing pulse for counting a delayed clock pulse from said coarse stepsize delay line to produce a count, and producing a second timing pulse when the count reaches a predetermined value, said second timing pulse defining the end timing of each of said longer intervals; and

a latch, responsive to said second timing pulse, for latching and forwarding a first, second and third groups of delay control bits to said coarse stepsize delay line as said higher significant bits and latching and forwarding the fourth group of control bits to said fine stepsize delay line as said lower significant bits.