Information processing apparatus

• US 5,604,840 A
• Filed: 03/29/1993
• Issued: 02/18/1997
• Est. Priority Date: 10/25/1989
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamada, Minoru, Yagyu, Masayoshi, Masuda, Noboru, Yasunaga, Moritoshi, Shibata, Katsunari, Asai, Mitsuo
• Primary Examiner(s): Downs, Robert W.
• Application Number:
  US08/038,839
• Time in Patent Office: 1,422 Days
• Field of Search: 395/11, 395/27, 395/800
• US Class Current: 706/10
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

Claims

1. An information processing apparatus comprising:

an input bus for transmitting input data;

an output bus for transmitting output data;

an address bus for transmitting an address;

a command bus for transmitting a command;

a plurality of neuron processors connected to said buses, each processor, being selectable by an address, operates in accordance with a command, subjects input data to weighting by weigh values and calculations of accumulated addition and outputs output data to said output bus;

a rewritable first memory for storing a control command for controlling said neuron processors;

control means for selecting a processor subjected to an operation from said processors, by outputting an address to said address bus and outputting said control command stored in said first memory to said command bus;

a second memory for storing said input data from said input bus, and said output data from said output bus; and

a control device for controlling said neuron processors by inputting at least said input data and said control command from a host computer;

wherein a number and connections of said neuron processors are changed by rewriting said control command stored in said first memory.

2. An information processing apparatus comprising:

an input bus for transmitting input data;

an output bus for transmitting output data;

an address bus for transmitting an address;

a command bus for transmitting a command;

a plurality of neuron processors connected to said buses, each processor, being selectable by an address, operates in accordance with a command, subjects input data to weighting by weigh values and calculations of accumulated addition and outputs output data to said output bus;

a rewritable first memory for storing a control command for controlling said neuron processors;

control means for selecting a processor subjected to an operation from said processors, by outputting an address to said address bus and outputting said control command stored in said first memory to said command bus;

a second memory for storing said input data from said input bus, and said output data from said output bus; and

a control device for controlling said neuron processors by inputting at least said input data and said control command from a host computer;

wherein a learning method and a number of learning operations regarding said neuron processors are controlled by rewriting said control command stored in said first memory.

3. An information processing apparatus comprising:

an input bus for transmitting input data;

an output bus for transmitting output data;

an address bus for transmitting an address;

a command bus for transmitting a command;

a plurality of neuron processors connected to said buses, each processor, being selectable by an address, operates in accordance with a command, subjects input data to weighting by weigh values and calculations of accumulated addition and outputs output data to said output bus;

a rewritable first memory for storing a control command for controlling said neuron processors;

control means for selecting a processor subjected to an operation from said processors, by outputting an address to said address bus and outputting said control command stored in said first memory to said command bus;

a second memory for storing said input data from said input bus, and said output data from said output bus; and

a control device for controlling said neuron processors by inputting at least said input data and said control command from a host computer;

a first board provided with said neuron processors; and

a second board provided with said control device,

wherein said first board is connected to said second board through said input bus, said output bus, said address bus and said command bus.

4. An information processing apparatus according to claim 3, wherein teacher data is stored in said second memory, and in said neuron processors, learning is performed in accordance with said teacher data.

5. An information processing apparatus comprising:

a neural network of neuron processors comprising;

an input layer,

an intermediate layer,

an output layer,

first means for holding a first weighting value corresponding to an output value from said input layer, wherein said output value is determined in an order of said input layer, said intermediate layer and said output layer in an output operation,

second means for holding a second weighting value corresponding to a learning signal value from said output layer, wherein said learning signal value is determined in an order of said output layer, said intermediate layer and said input layer in a learning operation, and

modification means for modifying said first weighting value and said second weighting value to a same value by said learning operation,

wherein said learning signal value is calculated in parallel in each of said neuron processors by supplying said second weighting value to each of said neuron processors; and

communication means for performing broadcast communications among said neuron processors.

6. An information processing apparatus comprising:

an input bus for transmitting input data;

an output bus for transmitting output data;

an address bus for transmitting an address;

a command bus for transmitting a command;

a neural network of neuron processors connected to said buses, each neuron processor, being selectable by an address, operates in accordance with a command, subjects input data to weighing by weigh values and calculations of accumulated addition and outputs output data to said output bus;

said neural network of neuron processors comprises;

an input layer,

an intermediate layer,

an output layer,

first means for holding a first weighing value corresponding to an output value from said input layer, wherein said output value is determined in an order of said input layer, said intermediate layer and said output layer in an output operation,

second means for holding a second weighing value corresponding to said learning signal from said output layer, wherein said learning signal value is determined in an order of said output layer, said intermediate layer and said input layer in a learning operation, and

modification means for modifying said first weighing value and said second weighing value to a same value by said learning operation;

a rewritable first memory for storing a control command for controlling said neuron processors;

control means for selecting a neuron processor subjected to an operation from said neuron processors, by outputting an address to said address bus and outputting said control command stored in said first memory to said command bus;

a second memory for storing said input data from said input bus, and said output data from said output bus; and

a control device for controlling said neuron processors by inputting at least said input data and said control command from a host computer;

wherein a number and connections of said neuron processors are changed by rewriting said control command stored in said first memory.

7. An information processing apparatus comprising:

an input bus for transmitting input data;

an output bus for transmitting output data;

an address bus for transmitting an address;

a command bus for transmitting a command;

a neural network of neuron processors connected to said buses, each neuron processor, being selectable by an address, operates in accordance with a command, subjects input data to weighing by weigh values and calculations of accumulated addition and outputs output data to said output bus;

said neural network of neuron processors comprises;

an input layer,

an intermediate layer,

an output layer,

first means for holding a first weighing value corresponding to an output value from said input layer, wherein said output value is determined in an order of said input layer, said intermediate layer and said output layer in an output operation,

second means for holding a second weighing value corresponding to said learning signal from said output layer, wherein said learning signal value is determined in an order of said output layer, said intermediate layer and said input layer in a learning operation, and

modification means for modifying said first weighing value and said second weighing value to a same value by said learning operation;

a rewritable first memory for storing a control command for controlling said neuron processors;

control means for selecting a neuron processor subjected to an operation from said neuron processors, by outputting an address to said address bus and outputting said control command stored in said first memory to said command bus;

a second memory for storing said input data from said input bus, and said output data from said output bus; and

a control device for controlling said neuron processors by inputting at least said input data and said control command from a host computers,

wherein a learning method and a number of learning operations regarding said neuron processors are controlled by rewriting said control command stored in said first memory.

8. An information processing apparatus comprising:

an input bus for transmitting input data;

an output bus for transmitting output data;

an address bus for transmitting an address;

a command bus for transmitting a command;

a neural network of neuron processors connected to said buses, each neuron processor, being selectable by an address, operates in accordance with a command, subjects input data to weighing by weigh values and calculations of accumulated addition and outputs output data to said output bus;

said neural network of neuron processors comprises;

an input layer,

an intermediate layer,

an output layer,

first means for holding a first weighing value corresponding to an output value from said input layer, wherein said output value is determined in an order of said input layer, said intermediate layer and said output layer in an output operation,

second means for holding second weighing value corresponding to said learning signal from said output layer, wherein said learning signal value is determined in an order of said output layer, said intermediate layer and said input layer in a learning operation, and

modification means for modifying said first weighing value and said second weighing value to a same value by said learning operation;

a rewritable first memory for storing a control command for controlling said neuron processors;

control means for selecting a neuron processor subjected to an operation from said neuron processors, by outputting an address to said address bus and outputting said control command stored in said first memory to said command bus;

a second memory for storing said input data from said input bus, and said output data from said output bus;

a control device for controlling said neuron processors by inputting at least said input data and said control command from a host computer;

a first board provided with said neuron processors; and

a second board provided with said control device,

wherein said first board is connected to said second board through said input bus, said output bus, said address bus and said command bus.

9. An information processing apparatus according to claim 8, wherein teacher data is stored in said second memory, and in said neuron processors, learning is performed in accordance with said teacher data.