Method and apparatus for inserting computer code into a high level language (HLL) software model of an electrical circuit to monitor test coverage of the software model when exposed to test inputs

• US 5,604,895 A
• Filed: 09/29/1995
• Issued: 02/18/1997
• Est. Priority Date: 02/22/1994
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Raimi, Richard S.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): VU, VIET DUY
• Application Number:
  US08/536,420
• Time in Patent Office: 508 Days
• Field of Search: 395/500, 395/650, 395/700, 395/183.13, 395/183.11, 364/488, 364/489, 364/578
• US Class Current: 703/13
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

A method and apparatus, for determining test coverage estimation for an electrical circuit (10) formed in accordance with an original high level description (21), uses a central processing unit (CPU 18). The CPU (18) accesses the description (21) and parses the high level language description (21) to allow for the generation of new code. This new code is intermixed with code from the description (21) to form a new high level description (22) which not only can be used to simulate the electrical circuit but can collect test coverage information. A simulation of the description (22) is performed using test vector inputs to simulate operation of the circuit (10) and estimate it'"'"'s test coverage for the test vectors. Various warning/error messages are derived to indicate where the test vectors are lacking in test coverage.

Claims

1. A method for estimating test coverage of an original high level language description which represents an electrical circuit, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the method comprising the steps of:

parsing the original high level language description having at least one executable assignment statement to obtain information of the structure of the electrical circuit represented by the original high level language description; and

generating a new high level language description which includes both;

(1) new code generated in response to the step of parsing and (2) all the code of the original high level language description necessary for preserving the circuit behavior of the original high level language description;

executing the new high level language description via a central processing unit (CPU) in order to simulate the electrical circuit while providing binary test vectors as input to the simulation of the new high level language description;

storing, via the new code in the new high level language description, data which indicates whether, during the simulation of the new high level language description of the electrical circuit, the set of variables from the right side of the at least one executable assignment statement has been set to predetermined combinations of values to allow an acceptable level of test coverage of the electrical circuit.

2. The method of claim 1 wherein the step of generating further comprises:

using the new code to store data which indicates whether the at least one executable assignment statement has been executed.

3. The method of claim 1 wherein the at least one executable assignment statement comprises a plurality of executable assignment statements and the method further comprising the step of:

storing for each executable assignment statement in the plurality of executable assignment statements whether each assignment statement was executed, the storing being accomplished via the new high level language description.

4. The method of claim 1 wherein the step of generating comprises:

determining the predetermined combinations of gate input values such that all single stuck-at faults on a predetermined gate input of the original high level description will be propagated to a predetermined gate output of the original high level description when the new high level description is if executed with those gate input values.

5. The method of claim 1 wherein the step of generating comprises:

simulating the operation of an electrical circuit by executing the new high level description and inputting input data into the high level description, the electrical circuit being modeled by the new high level description operating on the input data.

6. The method of claim 5 wherein the step of simulating comprises:

storing at least one file of output data which stores results of the step of simulating.

7. The method of claim 5 wherein the step of simulating comprises:

storing multiple files of output data, each file of output data storing results resulting from the step of simulating.

8. The method of claim 5 wherein the step of simulating comprises:

storing a plurality of data vectors, each data vector within the plurality of data vectors identifies which portions of the electrical circuit were accurately tested by a specific test procedure.

9. The method of claim 1 wherein the step of generating comprises:

executing the new high level description using input data patterns

creating a output data file which identifies, for each input data pattern, which portions of the new high level description have been accurately tested by each data routine.

10. The method of claim 9 further comprising:

reducing the number of input data patterns needed to test the new high level description using the output data file to determine a desirable reduction.

11. The method of claim 1 wherein the step of generating comprises:

simulating the new high level description using input data patterns;

creating an output data file which identifies, for each input data pattern, the number of clock cycles required by each input data pattern and which portions of the new high level description have been accurately tested by each input data pattern.

12. The method of claim 11 further comprising:

reducing the number of input data patterns needed to test the new high level description by maximizing test coverage of the input data patterns.

13. The method of claim 11 further comprising:

reducing the number of input data patterns needed to test the new high level description by minimizing a total number of clock cycles needed to achieve a predetermined level of test coverage for the new high level description.

14. The method of claim 11 further comprising:

reducing the input data patterns such that an acceptable total number of test clock cycles is achieved along with an acceptable test coverage.

15. The method of claim 1 comprising:

executing the new high level description using input data patterns to gain test coverage information; and

using the test coverage information to develop a test procedure for testing the electrical circuit modeled by the new high level description.

16. The method of claim 1 wherein the step of generating comprises:

storing data which identifies whether the left side, which is subject to assignment, is set to both a true and false logic state.

17. The method of claim 1 wherein the step of generating comprises:

storing data which identifies when the left side, which is subject to assignment, completes at least one execution without changing value.

18. The method of claim 1 wherein the step of generating comprises:

storing data which identifies when the left side, which is subject to assignment, completes at least one execution without changing value to ensure that a low-power mode is efficient.

19. The method of claim 1 wherein the step of generating comprises:

storing output information from the simulation of an electrical circuit that implements a state machine wherein the output information may be used to determined if all reachable states in the state machine were entered when the new high level description was executed.

20. The method of claim 1 wherein the step of generating comprises:

storing output information from the simulation of an electrical circuit which implements a state machine wherein the output information may be used to determined if all transitions between states in the state machine were traversed when the new high level description was executed.

21. The method of claim 1 wherein the step of generating comprises:

providing warning or error messages which identify portions of the new high level description that were not tested when a predetermined set of input data patterns was applied to the new high level description during simulation.

22. The method of claim 1 further comprising:

executing the new high level language description to create a plurality of output data files which contain test coverage information; and

merging the plurality of output data files into one global data file which is used to obtain test coverage information pertaining to a set of input data patterns applied during simulation of the new high level language description which models the electrical circuit.

23. A data processor for determining the test coverage of an electrical circuit, the data processor comprising:

a memory unit containing an original high level description which models the electrical circuit via a plurality of assignment statements, each assignment statement having a left side and a right side wherein the left side and right side are separated by an assignment operator, the right side containing at least one binary variable;

a bus coupled to the memory unit; and

a central processing unit (CPU) coupled to the bus to allow communication between the CPU and the memory unit, the CPU reading the original high level language description from the memory unit and creating a new high level language description containing the plurality of assignment statements and a plurality of new assignment statements inserted among the plurality of assignment statements to store test coverage information in an output file in the memory unit, the CPU determining, based upon simulation of the new high level language description using a set of input binary test data patterns, the test coverage information wherein the test coverage information includes;

(1) whether the at least one variable on the right side of each assignment statement in the plurality of assignment statements has been set to a plurality of predetermined values;

(2) whether the left side of each assignment statements in the plurality of assignment statements has been set to a predetermined set of values; and

(3) whether each of the assignment statements in the plurality of assignments statements has been executed.

24. The data processor of claim 23 wherein the set of input data patterns contain a plurality of data patterns, the output file being analyzed by the CPU to determine which data patterns are redundant and contribute nothing new to test coverage of the electrical circuit.

25. The data processor of claim 24 wherein a subset of input data patterns which are redundant and contribute nothing new to test coverage of the electrical circuit are identified as being data patterns which may be removed from the set of data patterns to form a new set of data patterns, the determining of which data patterns are redundant and contribute nothing new to test coverage of the electrical circuit being performed in a manner which both:

(1) reduces the number of clock cycles the new set of data patterns requires to execute in comparison to the set of data patterns; and

(2) reduces the number of data patterns residing within the new set of data patterns as compared to the set of data patterns.

26. The data processor of claim 23 wherein the plurality of new assignment statements inserted among the plurality of assignment statements are also used to indicate which left side of the assignments statements in the plurality of assignments statements stay at a single logic value for a predetermined amount of time.

27. The data processor of claim 23 wherein the plurality of new assignment statements inserted among the plurality of assignment statements are also used to indicate which states of a state machine modeled within the original high level language description have been entered during simulation of the new high level language description.

28. The data processor of claim 23 wherein the plurality of new assignment statements inserted among the plurality of assignment statements are also used to indicate which state transitions of a state machine modeled within the original high level language description have been taken during simulation of the new high level language description.

29. A method for determining the test coverage of a plurality of test inputs, the method comprising the steps of:

providing an original high level description model of an electrical circuit, the original high level description model having a plurality of assignments statements each of which have a first portion which is subject to assignment from a second portion wherein the second portion contains variables and logical operators;

parsing the original high level description model to allow for the generation of new assignments statements using information obtained from the parsing;

inserting the new assignments statements into at least a portion of the original high level description model to create a new high level description model;

executing in a simulator the new high level description model wherein some of the new assignments statements in the new high level description model create an output file which contains information regarding;

(1) whether the first portion of an assignment statements in the plurality of assignments statement has been transitioned to both a true value and a false value; and

(2) whether the second portion of each assignments statements in the plurality of assignments statements has been transitioned to all logical combinations in a predetermined set of combinations; and

generating a warning/error message file in response to the output file, the warning/error message file identifying possible voids in test coverage of the electrical circuit.

30. A test estimator for estimating test coverage of an original high level language description of an electrical circuit given a set of test vectors as input, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the test estimator comprising:

means for parsing the original high level language description to obtain information of the general structure of the high level language description and information of the structure of the at least one executable assignment statement; and

means for generating a new high level language description which includes new generated code and all the code of the original high level language description necessary for preserving a circuit behavior of the original high level description, the means for generating creating the new high level language description in response to the information obtained by the means for parsing, the new generated code being generated by the means for generating to store data which indicates whether, during the simulation of the new high level language description of the circuit, the set of variables from the right side of the at least one executable assignment statement has been set to predetermined combinations of values in response to a plurality of binary test vectors applied as input to various input terminals which are simulated as being part of the electrical circuit modeled by the new high level language description.

31. A test estimator for determining the test coverage of a plurality of test input vectors, the test estimator comprising:

means for accessing a high level description model of an electrical circuit, the high level description model having a plurality of assignments statements each of which have a first portion which is subject to assignment from a second portion wherein the second portion contains variables and logical operators;

means for parsing the high level description model to allow for the generation of new assignments statements by using information obtained by the parsing;

means for inserting the new assignments statements into the high level description model to create a new high level description model;

means for executing the new high level description model wherein some of the new assignments statements in the new high level description model create an output file which contains information regarding;

(1) whether the first portion of an assignment statements in the plurality of assignments statement has been transitioned to both a true value and a false value; and

(2) whether the second portion of each assignments statements in the plurality of assignments statements has been transitioned to all logical combinations in a predetermined set of binary combinations; and

means for generating a warning/error message file in response to the output file, the warning/error message file identifying possible voids in test coverage of the electrical circuit.

32. A method for determining test coverage, the method comprising the steps of:

providing a plurality of test vectors where each test vector in the plurality of test vectors contains a plurality of binary values which, when applied to an integrated circuit, test at least a portion of the integrated circuit to ascertain whether the at least a portion of the integrated circuit is operating properly;

providing a plurality of simulation instructions wherein the plurality of simulation instructions, when executed, simulate an operation of the integrated circuit, each simulation instruction in the plurality of simulation instructions having an assignment portion and a calculation portion wherein the calculation portion is processed, when executed, to assign a binary value to the assignment portion, the plurality of simulation instructions simulating input terminals of an external portion of the integrated circuit;

parsing the plurality of simulation instructions to form parsed information;

processing the parsed information to determine which test instructions need to be inserted into the plurality of simulation instructions;

inserting the test instructions into the plurality of simulation instructions;

executing the plurality of instructions, which includes the test instructions, using the test vectors as input to the simulated input terminals within the plurality of instructions;

storing test data while executing via the test instructions; and

using the test data to determine the test coverage of the test vectors.

33. A method for determining transitions in an electrical circuit simulation of an electrical circuit, the method comprising the steps of:

providing a plurality of test vectors containing a plurality of binary values which are used to test the functionality of the electrical circuit;

providing a plurality of instructions which are used to model the operation of the electrical circuit via binary assignment statements which simulate logic gates;

parsing the binary assignment statements to obtain assignment information;

using the assignment information to insert a set of proper test instructions among the binary assignment statements;

executing the binary assignment statements, which include the test instructions, while providing the plurality of test vectors to the binary assignments statements, wherein the test instructions monitor binary switching in the binary assignment statements and record switching data to storage media, the binary switching simulating the electrical circuit; and

accessing the storage media to evaluate the switching data to determine an extent of test coverage of the electrical circuit when using the plurality of test vectors.

34. The method of claim 33 wherein the step of accessing comprises:

altering the plurality of test vectors in order to improve the test coverage of the plurality of test vectors when the plurality of test vectors are used to test the electrical circuits which are manufactured.

35. The method of claim 33 further comprising the steps of:

manufacturing a plurality of integrated circuits which contain the electrical circuit;

testing each integrated circuit in the plurality of integrated circuits using the plurality of test vectors.

36. A method for determining whether binary test vectors applied to a software model of an electrical circuit cause a propagation of a single stuck-at fault from an input of a modeled logic gate to an output of the modeled logic gate wherein the software model models the modeled logic gate, the method comprising the steps of:

providing the binary test vectors containing a plurality of binary values which are used to test the functionality of the electrical circuit;

providing a plurality of instructions which are used to simulate the electrical circuit and the modeled logic gates via binary assignment statements which simulate logic gates;

parsing the binary assignment statements to obtain assignment information, the assignment information being used to determine predetermined combinations of gate input values such that all single stuck-at faults on a predetermined gate input of the modeled logic gates will be propagated to a predetermined gate output of the modeled logic gates when the modeled logic gates are simulated with these gate input values;

using the assignment information to insert a set of test instructions among the binary assignment statements, the set of test instructions being used to monitor the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate;

executing the binary assignment statements, which include the test instructions, while providing the binary test vectors as input, wherein the test instructions monitor the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate; and

determining the extent to which binary test vectors applied to the software model of the electrical circuit cause the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate wherein the software model models the modeled logic gate.