Two-line mixed analog/digital bus system and a master station and a slave station for use in such system
First Claim
1. A two-wire multi-station bus system comprising:
- a clock wire and a data wire;
at least one slave station, each slave station having a slave clock terminal connected to the clock wire and a slave data terminal connected to the data wire, address recognition means for recognizing a digital slave address pertaining to an associated slave station, and analog data generating means connected to the slave data terminal;
at least one master station having a master clock terminal connected to the clock wire and a master data terminal connected to the data wire, clock signal generating means and clock signal control means connected to the master clock terminal, and digital address generating means and analog signal receiving means connected to the master station data terminal;
said master station having master station control means for generating said digital slave address under synchronization by clock signals generated on said master clock terminal, followed by a finite interval of time wherein said clock signal control means control a binary hold signal on said clock wire, while enabling said analog signal receiving means; and
said slave station having slave station control means for, under control of said digital slave address received on said slave station terminal and said binary hold signal received on said slave station clock terminal, enabling said analog data generating means until detecting termination of said finite interval as represented by said binary hold signal.
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Accused Products
Abstract
A two-line multi-station bus system has a clock wire and a data wire and supports selective slave station addressing by a prevalent master station for thereupon eliciting a bitwise clocked data transfer between the clocking master station and an addressed and clocked slave station. Moreover, the system supports analog signal transfer in that the prevalent master station has a holding member for while eliciting the analog signal from the actual addressed slave station holding said clocking through carrying the clock wire at a predetermined binary value. The analog signal is received until changeover of the clock wire to a binary value other than the predetermined binary value a particular version the analog signal is pulse width modulated in combination with associate delimiting signals on the clock wire sent by the transmitter station that is not necessarily the master station.
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Citations
16 Claims
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1. A two-wire multi-station bus system comprising:
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a clock wire and a data wire; at least one slave station, each slave station having a slave clock terminal connected to the clock wire and a slave data terminal connected to the data wire, address recognition means for recognizing a digital slave address pertaining to an associated slave station, and analog data generating means connected to the slave data terminal; at least one master station having a master clock terminal connected to the clock wire and a master data terminal connected to the data wire, clock signal generating means and clock signal control means connected to the master clock terminal, and digital address generating means and analog signal receiving means connected to the master station data terminal; said master station having master station control means for generating said digital slave address under synchronization by clock signals generated on said master clock terminal, followed by a finite interval of time wherein said clock signal control means control a binary hold signal on said clock wire, while enabling said analog signal receiving means; and said slave station having slave station control means for, under control of said digital slave address received on said slave station terminal and said binary hold signal received on said slave station clock terminal, enabling said analog data generating means until detecting termination of said finite interval as represented by said binary hold signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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- 8. A master station for use in a two-line multi-station bus system including a data bus, a clock bus and a plurality of slave stations, comprising a clock terminal coupled to said clock bus, a data terminal coupled to said data bus, means for addressing said plurality of slave stations over said clock bus and means for controlling said clock signal, said master station data terminal adapted to provide digital data and analog signal transfer, wherein analog signal transfer occurs when said master station addresses one of said slave stations and said controlling means holds said clock bus until said master station terminates signal transfer by terminating the holding of the clock bus.
- 13. A slave station for use in a two-line multi-station bus system including a data bus, a clock bus and a master station, comprising a clock terminal coupled to said clock bus, a data terminal coupled to said data bus and slave station address detector means for detecting the presence of a predetermined address and responding by producing a bitwise clocked data stream on said data bus, and clock holding detector means for detecting a clock hold condition on said clock bus through pullup of said clock bus to a predetermined binary value and transmitting means for then transmitting an analog signal on said data bus until said clock bus is changed from the predetermined binary value.
Specification