Monolithic micromechanical vibrating beam accelerometer with trimmable resonant frequency

• US 5,605,598 A
• Filed: 05/13/1994
• Issued: 02/25/1997
• Est. Priority Date: 10/17/1990
• Status: Expired due to Term

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Greiff, Paul
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/242,274
• Time in Patent Office: 1,019 Days
• Field of Search: 156/628.1, 156/630.1, 156/633.1, 156/643.1, 156/644.1, 156/647.1, 156/657.1, 156/659.11, 156/662.1, 437/228, 437/233, 437/245, 437/238, 216/2, 216/33, 216/67, 216/79, 216/41, 216/56, 216/62
• US Class Current: 438/50
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/097 by vibratory elements
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: G01P 2015/0831 the mass being of the paddle type having the pivot axis between the longitudinal ends of the mass, e.g. see-saw configuration

Abstract

A monolithic, micromechanical vibrating beam accelerometer with a trimmable resonant frequency is fabricated from a silicon substrate which has been selectively etched to provide a resonant structure suspended over an etched pit. The resonant structure comprises an acceleration sensitive mass and at least two flexible elements having resonant frequencies. Each of the flexible elements is disposed generally collinear with at least one acceleration sensitive axis of the accelerometer. One end of at least one of the flexible elements is attached to a tension relief beam for providing stress relief of tensile forces created during the fabrication process. Mass support beams having a high aspect ratio support the mass over the etched pit while allowing the mass to move freely in the direction collinear with the flexible elements. Also disclosed is a method for fabricating such an accelerometer. Further disclosed is an alternative embodiment of the aforementioned accelerometer characterized by a low profile, and alternative planar processing methods for fabrication of these and other embodiments.

Claims

1. A method of fabricating a semiconductor transducer including the steps of:

providing a first semiconductor substrate having an etch resistant first surface;

providing a second semiconductor substrate with a precursor portion and a second portion, and bonding said second portion to said etch resistant first surface of said first substrate;

removing said precursor portion;

selectively diffusing said second portion to define a plurality of electrodes and supports;

growing on said second portion a first epitaxial layer;

aperturing said first epitaxial layer above said support defining diffusions;

growing on said first epitaxial layer a second epitaxial layer;

removing selected portions of said second epitaxial layer to define a suspended portion; and

removing said first epitaxial layer.

2. The process of claim 1 wherein said step of removing selected portions of said second epitaxial layer includes reactive ion etching.

3. The process of claim 1 wherein said step of removing said first epitaxial layer includes exposing said first epitaxial layer to ethylene-diamine-pyrocatechol-water.

4. A method for fabricating a monolithic micromechanical vibrating accelerometer with a trimmable resonant frequency, comprising the steps of:

providing a silicon substrate having an oxidized layer covering at least a portion of said silicon substrate;

removing selected regions of said oxidized layer;

etching said silicon substrate with an anisotropic etchant to form a pit having sidewalls and a bottom;

selectively doping the sidewalls and bottom of said pit in said silicon substrate through the regions of selectively removed oxidized layer, to form etch resistant regions in said silicon substrate; and

etching said silicon substrate with anisotropic etchant, said etching forming at least two silicon resonant structures including,

an acceleration sensitive mass having a center of gravity;

at least first and second flexible elements suspending said acceleration sensitive mass above an etched pit and substantially co-planar with a surface of said acceleration sensitive mass;

first and second tension relief elements attached to said first and second flexible elements;

first and second stabilizing elements; and

at least one sensing electrode disposed on said substrate, proximate said pit and substantially orthogonal to said acceleration sensitive mass.

5. The method of claim 4 further including between the step of selectively doping and etching to form said at least two resonant structures, the steps of:

growing silicon crystal material in regions of said silicon substrate, said oxidized layer of said regions having been removed and said regions having been selectively doped; and

capping said regions with an etch resistant layer to form an etch resistant mass.

6. A method for fabricating a transducer, comprising the steps of:

providing a first silicon substrate having a first dielectric surface;

disposing a second silicon wafer onto said first dielectric surface of said first silicon substrate, said second silicon wafer selectively doped with an etch resistant dopant;

depositing a third silicon layer on said selectively doped second silicon wafer;

forming a fourth doped silicon layer on selected regions of said third silicon layer; and

exposing said first silicon substrate, said second silicon wafer, said third silicon layer, and said fourth doped silicon layer to an etchant, said etchant removing portions of said second silicon wafer and said third silicon layer.

7. The method of claim 6 wherein said first silicon substrate is a P-type silicon substrate.

8. The method of claim 7 wherein said first dielectric surface is an oxide layer.

9. The method of claim 7 wherein said first dielectric surface is a nitride layer.

10. The method of claim 6 wherein said step of disposing said second silicon wafer onto said first dielectric surface comprises:

bonding a first surface of said second silicon wafer to said first dielectric surface, said second silicon wafer comprising an N-type electrode layer having said first surface of said second silicon wafer, and a P-type layer;

removing said P-type layer by electrochemical etching;

masking said N-type electrode layer exposed by removal of said P-type layer; and

selectively diffusing boron into at least one region of said N-type electrode layer defined by said masking step.

11. The method of claim 10 wherein said step of selectively diffusing boron into said at least one region creates an electrode in said at least one region.

12. The method of claim 10 wherein said step of selectively diffusing boron into said at least one region creates an anchor base portion in said at least one region.

13. The method of claim 10 wherein said bonding step includes annealing said second silicon wafer to said first dielectric surface.

14. The method of claim 6 wherein said step of depositing said third silicon layer on said selectively doped second silicon wafer comprises depositing an N-type epitaxial gap layer.

15. The method of claim 14 wherein said step of depositing said third silicon layer on said selectively doped second silicon wafer further comprises etching said third silicon layer to form at least one via to an underlying, etch resistant selectively doped region of said second silicon wafer.

16. The method of claim 14 wherein said deposition of said N-type epitaxial gap layer is to a thickness substantially equivalent to a desired electrode gap.

17. The method of claim 6 wherein said step of forming said fourth doped silicon layer on said selected regions of said third silicon layer comprises:

depositing an N-type epitaxial device layer onto said N-type epitaxial gap layer;

boron doping selected regions of said N-type epitaxial device layer;

selectively masking said N-type epitaxial device layer; and

patterning said N-type epitaxial device layer.

18. The method of claim 17 wherein said boron doped selected regions of said N-type epitaxial layer each include a concentration of germanium roughly equivalent to a concentration of boron.

19. The method of claim 17 wherein said patterning step comprises reactive ion etching said N-type epitaxial device layer to form elements of said sensor.

20. The method of claim 6 wherein said etchant is an ethylene-diamine-pyrocatechol-water (EDP) bath.

21. A method of fabricating a semiconductor transducer including the steps of:

providing a first semiconductor substrate having an etch resistant first surface;

providing a second semiconductor substrate with a precursor portion and a second portion, and bonding said second portion to said etch resistant first surface of said first substrate;

removing said precursor portion;

selectively diffusing said second portion to define a plurality of doped electrodes and supports, and undoped regions;

growing on said second portion an epitaxial layer;

etching a pit in said epitaxial layer over each of selected support defining diffusions in said second portion;

selectively diffusing said epitaxial layer to define a suspended portion;

removing selected portions of said epitaxial layer; and

removing said undoped regions of said second portion.

22. The process of claim 21 wherein said step of removing selected portions of said epitaxial layer includes reactive ion etching.

23. The process of claim 21 wherein said step of removing said undoped regions of said second portion includes exposing said second portion to ethylene-diamine-pyrocatechol-water.

24. A method for fabricating a transducer, comprising the steps of:

providing a first silicon substrate having a first dielectric surface;

disposing a second silicon wafer onto said first dielectric surface of said first silicon substrate, said second silicon wafer selectively doped with an etch resistant dopant;

depositing a third silicon layer on said selectively doped second silicon wafer;

doping and etching said third silicon layer; and

exposing said first silicon substrate, said second silicon wafer, and said third silicon layer to an etchant, said etchant removing portions of said second silicon wafer.

25. The method of claim 24 wherein said first silicon substrate is a P-type silicon substrate.

26. The method of claim 25 wherein said first dielectric surface is an oxide layer.

27. The method of claim 25 wherein said first dielectric surface is a nitride layer.

28. The method of claim 24 wherein said step of disposing said second silicon wafer onto said first dielectric surface comprises:

bonding a first surface of said second silicon wafer to said first dielectric surface, said second silicon wafer comprising an N-type electrode layer having said first surface of said second silicon wafer, and a P-type layer;

removing said P-type layer by electrochemical etching;

masking said N-type electrode layer exposed by removal of said P-type layer; and

selectively diffusing boron into at least one region of said N-type electrode layer defined by said masking step.

29. The method of claim 28 wherein said step of selectively diffusing boron into said at least one region creates an electrode in said at least one region.

30. The method of claim 28 wherein said step of selectively diffusing boron into said at least one region creates an anchor base portion in said at least one region.

31. The method of claim 28 wherein said bonding step includes annealing said second silicon wafer to said first dielectric surface.

32. The method of claim 24 wherein said step of depositing said third silicon layer on said selectively doped second silicon wafer comprises depositing an N-type epitaxial layer.

33. The method of claim 32 wherein said step of doping and etching said third silicon layer comprises forming at least one pit above a respective underlying, etch resistant selectively doped region of said second silicon wafer.

34. The method of claim 33 wherein said step of doping and etching said third silicon layer further comprises selectively boron doping said third silicon layer to define transducer device elements.

35. The method of claim 34 wherein said step of boron doping said third silicon layer further comprises germanium doping said transducer device elements to a concentration generally equivalent to that of boron.

36. The method of claim 34 wherein said step of doping and etching said third silicon layer further comprises selectively masking and etching said third silicon layer.

37. The method of claim 36 wherein said masking and etching step includes reactive ion etching said third silicon layer.

38. The method of claim 24 wherein said etchant is an ethylene-diamine-pyrocatechol-water (EDP) bath.

39. A method of fabricating a semiconductor transducer including the steps of:

providing a first semiconductor substrate having an etch resistant first surface;

providing a second semiconductor substrate with a precursor portion and a second portion, and bonding said second portion to said etch resistant first surface of said first substrate;

removing said precursor portion;

etching at least one via through said second portion and said etch resistant first surface into said first semiconductor substrate;

selectively diffusing said second portion to define a plurality of doped electrodes and supports, and undoped regions;

growing on said second portion an epitaxial layer;

etching a pit in said epitaxial layer over each of selected support defining diffusions in said second portion;

selectively diffusing said epitaxial layer to define a suspended portion;

removing selected portions of said epitaxial layer; and

removing said undoped regions of said second portion.

40. The process of claim 39 wherein said step of removing selected portions of said epitaxial layer includes reactive ion etching.

41. The process of claim 39 wherein said step of removing said undoped regions of said second portion includes the steps of attaching said first semiconductor substrate to a source of positive electrical bias and exposing said first semiconductor substrate, said second semiconductor substrate and said epitaxial layer to a negatively charged electrochemical etchant.

42. The process of claim 41 wherein said electrochemical etchant is potassium hydroxide.

43. A method for fabricating a transducer, comprising the steps of:

providing a first silicon substrate having a first dielectric surface;

disposing a second silicon wafer onto said first dielectric surface of said first silicon substrate;

etching at least one via through said second silicon wafer and said first dielectric surface;

selectively doping said second silicon wafer with an etch resistant dopant;

depositing a third silicon layer on said selectively doped second silicon wafer;

doping and etching said third silicon layer; and

exposing said first silicon substrate, said second silicon wafer, and said third silicon layer to an etchant, said etchant removing portions of said second silicon wafer.

44. The method of claim 43 wherein said first silicon substrate is an N-type silicon substrate.

45. The method of claim 43 wherein said first dielectric surface is an oxide layer.

46. The method of claim 43 wherein said first dielectric surface is a nitride layer.

47. The method of claim 44 wherein said step of disposing said second silicon wafer onto said first dielectric surface comprises:

bonding a first surface of said second silicon wafer to said first dielectric surface, said second silicon wafer comprising an P-type electrode layer having said first surface of said second silicon wafer, and a N-type layer;

removing said N-type layer by lapping and polishing;

masking said P-type electrode layer exposed by removal of said N-type layer; and

selectively diffusing arsenic into at least one region of said P-type electrode layer defined by said masking step.

48. The method of claim 47 wherein said step of selectively diffusing arsenic into said at least one region creates an electrode in said at least one region.

49. The method of claim 47 wherein said step of selectively diffusing arsenic into said at least one region creates an anchor base portion in said at least one region.

50. The method of claim 47 wherein said bonding step includes annealing said second silicon wafer to said first dielectric surface.

51. The method of claim 47 wherein said step of depositing said third silicon layer on said selectively doped second silicon wafer comprises depositing a P-type epitaxial layer.

52. The method of claim 51 wherein said step of doping and etching said third silicon layer comprises forming at least one pit above a respective underlying, etch resistant selectively doped region of said second silicon wafer.

53. The method of claim 52 wherein said step of doping and etching said third silicon layer further comprises selectively phosphorous doping said third silicon layer to define transducer device elements.

54. The method of claim 53 wherein said step of doping and etching said third silicon layer further comprises selectively masking and etching said third silicon layer.

55. The method of claim 54 wherein said step of selectively masking and etching said third silicon layer includes reactive ion etching said third silicon layer.

56. The method of claim 43 wherein said step of exposing said first silicon substrate, said second silicon wafer, and said third silicon layer to an etchant comprises connecting said first silicon substrate to a source of positive electrical bias, and exposing said first silicon substrate, said second silicon wafer, and said third silicon layer to a negatively charged electrochemical etchant.

57. The method of claim 56 wherein said electrochemical etchant is potassium hydroxide.

58. The method of claim 57 wherein the step of exposing to an etchant further comprises etching through said third silicon layer and said second silicon wafer to physically separate said transducer device elements from said at least one via.

59. A method of fabricating a semiconductor transducer including the steps of:

providing a first semiconductor substrate having an etch resistant first surface;

providing a second semiconductor substrate with a precursor portion and a second portion, and bonding said second portion to said etch resistant first surface of said first substrate;

removing said precursor portion;

etching at least one via through said second portion and said etch resistant first surface into said first semiconductor substrate;

selectively diffusing said second portion to define a plurality of doped electrodes and supports, and undoped regions;

growing on said second portion a first epitaxial layer;

etching an aperture in said first epitaxial layer over each of selected support defining diffusions in said second portion;

growing on said first epitaxial layer a second epitaxial layer;

selectively diffusing said second epitaxial layer to define a suspended portion;

removing selected portions of said epitaxial layer; and

removing said undoped regions of said second portion and said first epitaxial layer.

60. The process of claim 59 wherein said step of removing selected portions of said second epitaxial layer includes reactive ion etching.

61. The process of claim 59 wherein said step of removing said undoped regions of said second portion and said first epitaxial layer includes the steps of attaching said first semiconductor substrate to a source of positive electrical bias and exposing said first semiconductor substrate, said second semiconductor substrate, said first epitaxial layer and said second epitaxial layer to a negatively charged electrochemical etchant.

62. The process of claim 61 wherein said electrochemical etchant is potassium hydroxide.

63. A method for fabricating a transducer, comprising the steps of:

providing a first silicon substrate having a first dielectric surface;

disposing a second silicon wafer onto said first dielectric surface of said first silicon substrate;

etching at least one via through said second silicon wafer and said first dielectric surface;

selectively doping said second silicon wafer with a first etch resistant dopant;

depositing a third silicon layer on said selectively doped second silicon wafer;

etching at least one aperture in said third silicon layer;

depositing a fourth silicon layer on said apertured third silicon layer;

doping and etching said fourth silicon layer; and

exposing said first silicon substrate, said second silicon wafer, said third silicon layer and said fourth silicon layer to an etchant, said etchant removing portions of said second '"'"'silicon wafer, and said third silicon layer.

64. The method of claim 63 wherein said first silicon substrate is an N-type silicon substrate.

65. The method of claim 63 wherein said first dielectric surface is an oxide layer.

66. The method of claim 63 wherein said first dielectric surface is a nitride layer.

67. The method of claim 63 wherein said step of disposing said second silicon wafer onto said first dielectric surface comprises:

bonding a first surface of said second silicon wafer to said first dielectric surface, said second silicon wafer comprising an P-type electrode layer having said first surface of said second silicon wafer, and a N-type layer;

removing said N-type layer by lapping and polishing.

68. The method of claim 67 wherein the step of selectively doping said second silicon wafer with a first etch resistant dopant includes masking said P-type electrode layer exposed by removal of said N-type layer, and selectively diffusing said first dopant into at least one region of said P-type electrode layer defined by said masking step.

69. The method of claim 68 wherein said first dopant is arsenic.

70. The method of claim 67 wherein said step of selectively diffusing arsenic into said at least one region creates an electrode in said at least one region.

71. The method of claim 67 wherein said step of selectively diffusing arsenic into said at least one region creates an anchor base portion in said at least one region.

72. The method of claim 67 wherein said bonding step includes annealing said second silicon wafer to said first dielectric surface.

73. The method of claim 63 wherein said step of depositing said third silicon layer on said selectively doped second silicon wafer comprises depositing a P-type epitaxial layer.

74. The method of claim 73 wherein said step of aperturing said third silicon layer includes the etching of said at least one aperture above said at least one selectively diffused region in said P-type electrode layer.

75. The method of claim 63 wherein said step of depositing said fourth silicon layer on said selectively doped second silicon wafer comprises depositing a P-type epitaxial layer.

76. The method of claim 75 wherein said step of doping and etching said fourth silicon layer further comprises selectively doping said fourth silicon layer with a second etch resistant dopant to define transducer device elements.

77. The method of claim 76 wherein said second etch resistant dopant is phosphorous.

78. The method of claim 75 wherein said step of doping and etching said fourth silicon layer further comprises selectively masking and etching said fourth silicon layer.

79. The method of claim 75 wherein said step of selectively masking and etching said third silicon layer includes reactive ion etching said third silicon layer.

80. The method of claim 63 wherein said step of exposing said first silicon substrate, said second silicon wafer, said third silicon layer and said fourth silicon layer to an etchant comprises connecting said first silicon substrate to a source of positive electrical bias, and exposing said first silicon substrate, said second silicon wafer, said third silicon and said fourth silicon layer to a negatively charged electrochemical etchant.

81. The method of claim 80 wherein said electrochemical etchant is potassium hydroxide.

82. The method of claim 81 wherein the step of exposing to an etchant further comprises etching through said third silicon layer and said second silicon wafer to physically separate said transducer device elements from said at least one via.