Inspecting method for semiconductor devices

• US 5,605,844 A
• Filed: 03/27/1996
• Issued: 02/25/1997
• Est. Priority Date: 03/31/1995
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Oki, Shinichi, Nakata, Yoshiro, Nagao, Koichi
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/624,954
• Time in Patent Office: 335 Days
• Field of Search: 437/8, 437/212, 437/226, 148/DIG. 12, 148/DIG. 28, 148/DIG. 162
• US Class Current: 438/17
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68322 Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/16 of an individual bump connector

Abstract

A semiconductor wafer is affixed on a dicing sheet having an appropriate expansibility. Then, a dicing operation is performed on the semiconductor wafer without dividing the dicing sheet, thereby dividing a plurality of semiconductor chips from each other. After aligning a contactor against the semiconductor wafer, the semiconductor wafer is fixed to the contactor. In this case, protrusions provided on the contactor are inserted into the gap between semiconductor chips. The protrusions cause a shift movement toward the peripheral edge of the contactor in response to thermal expansion of the contactor, thereby expanding the gap between semiconductor chips. Then a burn-in is performed on all of the plural semiconductor chips of which gap is expanded.

Claims

1. An inspecting method for a semiconductor device, comprising:

a first step of fixing a semiconductor wafer on an expandable sheet, said semiconductor wafer being formed with a plurality of semiconductor chips each having a test electrode;

a second step of dividing said plural semiconductor chips from each other by dicing said semiconductor wafer fixed on said sheet without dividing said sheet;

a third step of aligning a contactor for supplying an electric signal to said test electrode of each semiconductor chip against said semiconductor wafer after performing said dicing operation, and fixing said semiconductor wafer to said contactor; and

a fourth step of heating said semiconductor wafer fixed to said contactor so as to expand a gap between adjacent semiconductor chips in response to thermal expansion of said contactor, and then performing a burn-in on all of said plural semiconductor chips.

2. The inspecting method for a semiconductor device defined by claim 1, further comprising

a fifth step of performing a before-shipment inspection on each of said plural semiconductor chips subjected to said burn-in.

3. The inspecting method for a semiconductor device defined by claim 1, further comprising, between said second step and said third step,

a step of judging whether each semiconductor chip is defective or not and removing said each semiconductor chip from said sheet when said each semiconductor is judged to be defective.

4. The inspecting method for a semiconductor device defined by claim 1, further comprising, before said first step, a step of heating said sheet to contract said sheet.

5. The inspecting method for a semiconductor device defined by claim 1, wherein

said first step includes a step of fixing said sheet fixed to said semiconductor wafer on a substrate having substantially the same thermal expansion coefficient as that of said contactor.

6. The inspecting method for a semiconductor device defined by claim 5, wherein

said first step includes a step of fixing said sheet fixed to said semiconductor wafer on said substrate by a suction force.

7. The inspecting method for a semiconductor device defined by claim 6, wherein

said first step includes a step of fixing said sheet fixed to said semiconductor wafer on said substrate by said suction force acting from a suction hole formed in a specific region on said substrate where said suction hole does not confront with said test electrode formed on said semiconductor chip.

8. The inspecting method for a semiconductor device defined by claim 1, further comprising, before said first step, a step of providing protrusions on said contactor along a scribe line of said semiconductor wafer,

wherein said third step includes a step of inserting said protrusions of said contactor into each gap between adjacent semiconductor chips;

and

said fourth step includes a step of expanding said gap between said adjacent semiconductor chips by utilizing thermal expansion of said protrusions which shift toward a peripheral edge of said contactor in response to thermal expansion of said contactor itself.

9. The inspecting method for a semiconductor device defined by claim 1, further comprising, before said first step, a step of providing probe terminals on said contactor being engageable with and arranged at a position corresponding to the test electrodes formed on said semiconductor chips, respectively,

wherein said third step includes a step of coupling each probe terminal of said contactor with said corresponding test electrode of said semiconductor chip;

and

said fourth step includes a step of expanding said gap between said adjacent semiconductor chips by utilizing thermal expansion of said probe terminals which shift toward a peripheral edge of said contactor in response to thermal expansion of said contactor itself.

10. An inspecting method for a semiconductor device, comprising:

a first step of fixing a semiconductor wafer on a substrate, said semiconductor wafer being formed with a plurality of semiconductor chips each having a test electrode, said substrate having substantially the same thermal expansion coefficient as that of a contactor which has probe terminals each supplying an electric signal to said test electrode of each semiconductor chip;

a second step of dividing said plural semiconductor chips by dicing said semiconductor wafer fixed on said substrate without dividing said substrate;

a third step of aligning said contactor against said semiconductor wafer subjected to said dicing operation, and bringing said test electrode of each semiconductor chip into contact with a corresponding probe terminal of said contactor; and

a fourth step of heating said semiconductor wafer fixed to said substrate so as to expand a gap between adjacent semiconductor chips in response to thermal expansion of said substrate, and then performing a burn-in on all of said plural semiconductor chips.

11. The inspecting method for a semiconductor device defined by claim 10, further comprising

a fifth step of performing a before-shipment inspection on each of said plural semiconductor chips subjected to said burn-in.

12. The inspecting method for a semiconductor device defined by claim 10, further comprising, between said second step and said third step, a step of judging whether each semiconductor chip is defective or not and removing said each semiconductor chip when said each semiconductor is judged to be defective.

13. The inspecting method for a semiconductor device defined by claim 10, wherein

said first step includes a step of fixing said semiconductor wafer on said substrate by bond.

14. The inspecting method for a semiconductor device defined by claim 10, wherein

said first step includes a step of fixing said semiconductor wafer to said substrate, interposing an expandable sheet.

15. The inspecting method for a semiconductor device defined by claim 10, wherein

said first step includes a step of fixing said semiconductor wafer to said substrate by a suction force.

16. The inspecting method for a semiconductor device defined by claim 15, wherein

said first step includes a step of interposing a porous sheet between said sheet and said substrate.

17. The inspecting method for a semiconductor device defined by claim 15, wherein

said first step includes a step of fixing said semiconductor wafer to said substrate by a suction force acting from a suction hole formed in a specific region on said substrate where said suction hole does not confront with said test electrode formed on said semiconductor chip.

18. The inspection method for semiconductor devices defined by claim 15, further comprising, before said first step, a step of forming a plurality of suction holes on said substrate, and interposing a sheet between said semiconductor wafer and said substrate, said sheet having through holes respectively corresponding to said plural semiconductor chips,

wherein said first step includes a step of fixing said semiconductor wafer to said substrate by a suction force acting from said through holes formed on said sheet and said suction holes of said substrate.