Method for fabricating high voltage transistor having trenched termination

• US 5,605,852 A
• Filed: 05/18/1995
• Issued: 02/25/1997
• Est. Priority Date: 07/23/1992
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Bencuya, Izak
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/444,336
• Time in Patent Office: 649 Days
• Field of Search: 437/40 DM, 437/41 DM, 437/67, 437/70, 437/41 RG, 437/40 RG
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts. The trenches advantageously eliminate the process sensitivity of using multi field ring terminations with low resistivity semiconductor material.

Claims

1. A method of forming a transistor structure in a substrate comprising the steps of:

forming in the substrate a field effect transistor including a doped deep body region and a gate electrode in a gate trench in the substrate;

forming a first doped annular region in the substrate laterally surrounding the field effect transistor;

forming a second doped annular region in the substrate spaced apart from and laterally surrounding the first doped annular region;

forming a first trench in the substrate laterally surrounding the field effect transistor and lying between the first and second annular doped regions; and

forming insulation in the trench;

wherein a depth and doping level of the first and second doped annular regions are the same as that of the deep body region and the depth and width of the first insulated trench are the same as that of the gate trench.

2. The method of claim 1,

wherein the first doped annular region, second doped annular region, and deep body region are formed simultaneously;

and

wherein the gate trench is formed simultaneously with the first trench.

3. The method of claim 2, further comprising the step of, simultaneously with forming the first and second doped annular regions, forming a third doped annular region in the substrate laterally surrounding the first and second doped annular regions.

4. The method of claim 3, further comprising the step of forming a third insulated trench in the substrate between the second and third doped annular regions.

5. The method of claim 1, wherein the first and second doped annular regions are field rings.

6. The method of claim 1, wherein the first and second doped annular regions extend into the substrate to a depth greater than that of the first trench.

7. The method of claim 1, further comprising the step of forming a conductive guard ring overlying the substrate and laterally surrounding the first and second doped annular regions.

8. The method of claim 1, wherein a width of the first trench is 1 to 2 microns.

9. A method of forming a transistor structure in a substrate comprising the steps of:

forming in the substrate a field effect transistor including a doped deep body region and a gate electrode in a gate trench;

forming a doped annular region in the substrate laterally surrounding the field effect transistor;

forming a second doped annular region in the substrate spaced apart from and laterally surrounding the first doped annular region;

forming a trench in the substrate laterally surrounding the field effect transistor and lying between the first and second annular doped regions; and

forming insulation in the trench;

wherein the first doped annular region, second doped annular region, and deep body region are formed simultaneously; and

wherein the gate trench is formed simultaneously with the trench.