Cryptographic apparatus with double feedforward hash function

• US 5,606,616 A
• Filed: 07/03/1995
• Issued: 02/25/1997
• Est. Priority Date: 07/03/1995
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Anderson, Candace, Sprunk, Eric, Moroney, Paul
• Primary Examiner(s): Buczinski, Stephen C.
• Assistant Examiner(s): WHITE, CARMEN D
• Application Number:
  US08/497,880
• Time in Patent Office: 603 Days
• Field of Search: 380/49, 380/25, 380/42, 380/29
• US Class Current: 380/29
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC

Abstract

Apparatus is provided for authenticating information using a double feedforward hash function to provide complementarity in the implementation of an encryption algorithm. A cryptographic processor has a first input for receiving plaintext, a second input for receiving a key and an output for outputting ciphertext generated by cryptographically processing the plaintext and key. A first circuit element is responsive to the ciphertext and plaintext for outputting a first ciphertext derivative. A second circuit element is responsive to at least a portion of the first ciphertext derivative and the key for outputting a second ciphertext derivative. The first and second circuit elements can be XOR gates. Alternatively, these elements can be provided using lookup tables. Subsequent cryptographic processor stages can be provided having a first input for receiving second plaintext, a second input for receiving the second ciphertext derivative as a key, and an output for outputting second ciphertext generated by cryptographically processing the second plaintext and the second ciphertext derivative. In an illustrated embodiment, the cryptographic processor is a DES processor.

Claims

1. Cryptographic apparatus comprising:

a cryptographic processor having a first input for receiving eight parallel bytes F₁ -F₈ of first input data, a second input for receiving eight parallel bytes S₁ -S₈ of second input data, and an output for outputting eight parallel bytes C₁ -C₈ of ciphertext generated by cryptographically processing said first and second input data;

first means for processing said ciphertext and said first input data to produce a first ciphertext derivative comprising eight parallel bytes FD₁ -FD₈ ; and

second means for processing said first ciphertext derivative and said second input data for outputting a second ciphertext derivative comprising eight parallel bytes SD₁ -SD₈ ;

wherein;

said first means logically processes each of said ciphertext bytes C₁ -C₈ with the like numbered first input data byte F₁ -F₈ to produce said first ciphertext derivative; and

said second means logically processes each of said first ciphertext derivative bytes FD₁ -FD₈ with the like numbered second input data byte S₁ -S₈ to produce said second ciphertext derivative.

2. Cryptographic apparatus in accordance with claim 1 wherein:

said first means comprise a nonlinear function for logically processing each of said ciphertext bytes C₁ -C₈ with the like numbered first input data byte F₁ -F₈ to produce said first ciphertext derivative; and

said second means comprise a nonlinear function for logically processing each of said first ciphertext derivative bytes FD₁ -FD₈ with the like numbered second input data byte S₁ -S₈ to produce said second ciphertext derivative.

3. Cryptographic apparatus in accordance with claim 2 wherein said nonlinear functions output one half the number of bits as are input thereto.

4. Cryptographic apparatus in accordance with claim 1 wherein said first means exclusively OR'"'"'s each of said ciphertext bytes C₁ -C₈ with the like numbered first input data byte F₁ -F₈ to produce said first ciphertext derivative;

and

said second means exclusively OR'"'"'s each of said first ciphertext derivative bytes FD₁ FD₈ with the like numbered second input data byte S₁ -S₈ to produce said second ciphertext derivative.

5. Cryptographic apparatus in accordance with claim 4 wherein said first means comprise a lookup table addressed by said first input data and said ciphertext to output the exclusive OR'"'"'s of the like numbered bytes thereof.

6. Cryptographic apparatus in accordance with claim 5 wherein said second means comprise a lookup table addressed by said second input data and said first ciphertext derivative to output the exclusive OR'"'"'s of the like numbered bytes thereof.

7. Cryptographic apparatus in accordance with claim 4 wherein said second means comprise a lookup table addressed by said second input data and said first ciphertext derivative to output the exclusive OR'"'"'s of the like numbered bytes thereof.

8. Cryptographic apparatus in accordance with claim 1 further comprising:

a second cryptographic processor stage having a first input for receiving eight parallel bytes of third input data, a second input for receiving said second ciphertext derivative, and an output for outputting eight parallel bytes of second ciphertext generated by cryptographically processing said third input data and said second ciphertext derivative.

9. Cryptographic apparatus in accordance with claim 8 wherein said cryptographic processors are DES processors.

10. Cryptographic apparatus in accordance with claim 1 wherein said cryptographic processor is a DES processor.

11. Cryptographic apparatus in accordance with claim 2 further comprising lookup tables for implementing the nonlinear functions of said first and second means.

12. Cryptographic apparatus comprising:

a cryptographic processor having a first input for receiving eight parallel bytes F₁ -F₈ of input data, a second input for receiving parallel bytes F₂ -F₈ of said first input data as a key, and an output for outputting seven parallel bytes C₁ -C₇ of ciphertext generated by cryptographically processing said input data and said key;

first means for logically processing each of the first seven input data bytes F₁ -F₇ with the succeeding input data byte F₂ -F₈, respectively, to produce seven bytes of feedforward data FF₁ -FF₇ ; and

second means for logically processing each of said feedforward data bytes FF₁ -FF₇ with the like numbered ciphertext byte C₁ -C₇ to produce a ciphertext derivative comprising seven parallel bytes D₁ -D₇.

13. Cryptographic apparatus in accordance with claim 12 wherein:

said first means comprise a nonlinear function for logically processing each of the first seven input data bytes F₁ -F₇ with the succeeding input data byte F₂ -F₈, respectively, to produce said seven bytes of feedforward data FF₁ -FF₇ ; and

said second means comprise a nonlinear function for logically processing each of said feedforward data bytes FF₁ -FF₇ with the like numbered ciphertext byte C₁ -C₇ to produce said ciphertext derivative comprising said seven parallel bytes D₁ -D₇.

14. Cryptographic apparatus in accordance with claim 13 wherein said nonlinear functions output one half the number of bits as are input thereto.

15. Cryptographic apparatus in accordance with claim 12 wherein:

said first means exclusively OR'"'"'s each of the first seven input data bytes F₁ -F₇ with the succeeding input data byte F₂ -F₈, respectively, to produce said seven bytes of feedforward data FF₁ -FF₇ ; and

said second means exclusively OR'"'"'s each of said feedforward data bytes FF₁ -FF₇ with the like numbered ciphertext byte C₁ -C₇ to produce said ciphertext derivative comprising said seven parallel bytes D₁ -D₇.

16. Cryptographic apparatus in accordance with claim 15 wherein said first means comprise a lookup table addressed by said first seven and succeeding input data bytes to output the exclusive OR'"'"'s thereof.

17. Cryptographic apparatus in accordance with claim 16 wherein said second means comprise a lookup table addressed by said feedforward data bytes and the like numbered ciphertext bytes to output the exclusive OR'"'"'s thereof.

18. Cryptographic apparatus in accordance with claim 15 wherein said second means comprise a lookup table addressed by said feedforward data bytes and the like numbered ciphertext bytes to output the exclusive OR'"'"'s thereof.

19. Cryptographic apparatus in accordance with claim 12 wherein said cryptographic processor is a DES processor.

20. Cryptographic apparatus in accordance with claim 13 further comprising lookup tables for implementing the nonlinear functions of said first and second means.